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Date: Thu, 21 Nov 1996 20:32:46 GMTServer: NCSA/1.4.2Content-type: text/html<html><head><title> Northwest Laboratory for Integrated Systems</title></head><BODY><CENTER><TABLE><TR><TD> <!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/uwseal.gif"></TD><TD> <H1>Northwest Laboratory <BR>for Integrated Systems</H1></TD><TD> <!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/lis-3d.gif" ALT="LIS: "></TD></TR></TABLE><address> <!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href="http://www.cs.washington.edu/"> Department of Computer Science & Engineering</a> <br> <!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href="http://www.washington.edu/">University of Washington</a>, Box 352350 <br> <!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><a href="http://www.cs.washington.edu/area/">Seattle, WA</a> 98195-2350 USA</address><p><HR><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/c-elmt.gif"><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/selftune.gif"><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/retiming.gif"><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/fpga.gif"><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/spbkboard.gif"><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/emb.gif"></CENTER><HR>The Department of Computer Science and Engineering at the University of Washington has been engaged in Very Large Scale Integration (VLSI) and Computer-Aided Design (CAD) research, development, and education since the late 1970s. Today, the Northwest Laboratory for Integrated Systems is the focus of a wide variety of VLSI architectures, embedded sytems,and CAD research.<hr><CENTER><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><A HREF="#curr"><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/curr.gif" ALT="[CURRENT RESEARCH PROJECTS]"></A><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><A HREF="#prev"><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/prev.gif" ALT="[PREVIOUS RESEARCH PROJECTS]"></A><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><A HREF="http://www.cs.washington.edu/research/projects/lis/www/papers1/"><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/paper.gif" ALT="[PAPER REPOSITORY]"></A><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><A HREF="http://www.cs.washington.edu/research/projects/lis/www/people.html"><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/peopleicon.gif" ALT="[RESEARCHERS]"></A></CENTER><HR><A NAME="curr"><H2>Current Research Projects</H2></A><TABLE BORDER><TR><TD ALGIN=CENTER><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/c-elmt.gif"> <H3>Asynchronous Circuits <BR>and Verification</H3></TD><TD><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><img alt="o" src="http://www.cs.washington.edu/research/projects/lis/www/neatstuff/blueball.gif"><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><a href="http://www.cs.washington.edu/research/projects/lis/oetools/www/index.html">Time Separation of Events</a>: Specification, synthesis, and verification of timed asynchronous circuits.<P><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><img alt="o" src="http://www.cs.washington.edu/research/projects/lis/www/neatstuff/blueball.gif"><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><a href="http://www.cs.washington.edu/homes/hauck/asynch.html"> Asynchronous Circuits:</A> <EM> Survey of current asynchronous design methodologies, as well as the first FPGA for asynchronous circuits.</EM></TD></TR><TR><TD><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/fpga.gif"><H3>FPGAs and Rapid-Prototyping</H3><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><IMG SRC="http://www.cs.washington.edu/research/projects/lis/www/pic/spbkboard.gif" ALIGN=RIGHT></TD><TD><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><img alt="o" src="http://www.cs.washington.edu/research/projects/lis/www/neatstuff/blueball.gif"><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><a href="http://www.cs.washington.edu/research/projects/lis/triptych/www/index.html">Triptych/Montage FPGA Architectures</a>: Development of the <em>Triptych</em> and <em>Montage</em> FPGA architectures, architectures with improved densities over current commercial FPGAs.<P><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><img alt="o" src="http://www.cs.washington.edu/research/projects/lis/www/neatstuff/blueball.gif"><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><a href="http://www.cs.washington.edu//research/projects/lis/springbok/www/index.html">Multi-FPGA Systems & Rapid-Prototyping</a>: Development of the <em>Springbok</em> Rapid-Prototyping System for Board-Level Designs, as well as partitioning, pin assignment, and routing topology work for general multi-FPGA systems.<P><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><img alt="o" src="http://www.cs.washington.edu/research/projects/lis/www/neatstuff/blueball.gif"><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><a href="http://www.cs.washington.edu/research/projects/lis/www/emerald/">Emerald - An Architecture-Adaptive Toolset for FPGAs</a>:
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