http:^^www.cs.rochester.edu^u^sandhya^

来自「This data set contains WWW-pages collect」· EDU^U^SANDHYA^ 代码 · 共 71 行

Date: Thursday, 21-Nov-96 21:01:53 GMT
Server: NCSA/1.3
MIME-version: 1.0
Content-type: text/html
Last-modified: Wednesday, 04-Sep-96 19:03:48 GMT
Content-length: 2801

<TITLE>Sandhya Dwarkadas's URCS Home Page</TITLE>

<!WA0><IMG ALIGN=TOP SRC="http://www.cs.rochester.edu/images/urcslogo.gif"> <!WA1><IMG ALIGN=TOP SRC="http://www.cs.rochester.edu/u/sandhya/sandhya.gif">
<H1>Sandhya Dwarkadas, URCS Faculty</H1>
<P>
<BLOCKQUOTE>
Assistant Professor<BR>
Computer Science Department<BR>
University of Rochester<BR>
Rochester, NY  14627-0226<BR>
[e-mail]<BR>
Phone [phone]; FAX [phone]<BR>
</BLOCKQUOTE>
<P>

<p>Sandhya Dwarkadas received the B.Tech. degree in Electrical Engineering
from the Indian Institute of Technology, Madras, India, in
1986, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering
from Rice University in 1989 and 1992, respectively.
<p>
From 1992-1996, she was a research scientist in the <!WA2><a href = "http://www.cs.ric
e.edu/">Computer Science
Department</a> at <!WA3><a href = "http://www.rice.edu/">Rice University</a>.
She has just joined the faculty in the Computer Science Department at
the University of Rochester as an assistant professor.
Her research interests include parallel and distributed computing,
computer architecture, networks, simulation methodology,
and performance evaluation. In particular, she is interested in
compiler and runtime support for parallelism, and parallel applications
research.
<p>
As a graduate student, she developed an efficient execution-driven technique
for the simulation of shared-memory multiprocessors. This technique was
implemented as part of the Rice Parallel Processing Testbed (RPPT).
She used this tool
to design and evaluate synchronization support, adaptive caching techniques,
and the use of relaxed consistency models for a hierarchical
bus-based shared-memory architecture.
These results contributed to the design of the Willow multiprocessor
architecture.
This work also lead to a classification of memory consistency models that,
in addition to unifying all existing models into a common framework,
provides insight into the implications of these models with respect to access
ordering.
<p>
She is currently involved in the design and implementation of <!WA4><a href = "http://
www.cs.rice.edu/CS/Systems/software/treadmarks.html">TreadMarks</a>,
a software distributed shared memory system running on a network of
workstations. She is developing compiler-runtime integration techniques
for improved performance.
She has also worked with Alejandro Schaffer on
<!WA5><a href="http://www.cs.rice.edu/~schaffer/fastlink.html"> FASTLINK</a>,
a project to provide fast sequential and parallel genetic linkage analysis
software.
<p>
Finger:
<!WA6><A HREF="http://cs.indiana.edu/finger/cs.rochester.edu/sandhya/w">
<CODE>[e-mail]</CODE></A>
<P>
<!WA7><A HREF="http://www.cs.rochester.edu/users/grads.html">
 <!WA8><IMG ALIGN=TOP SRC="http://www.cs.rochester.edu/images/up.gif">Back to URCS Faculty directory</A><P>
<!WA9><A HREF="http://www.cs.rochester.edu/urcs.html">
<!WA10><IMG ALIGN=TOP SRC="http://www.cs.rochester.edu/images/home.gif">Back to URCS Home Page</A><P>