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EDU^~JHAYES^
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Date: Mon, 25 Nov 1996 23:13:30 GMT
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<html><!BODY BACKGROUND="IMGS/backg.gif" TEXT="#FFFF00" LINK="FF0000" VLINK="00FF00"> <head><title> John P. Hayes </title></head><!WA0><IMG BORDER=1 ALIGN=center SRC="http://www.eecs.umich.edu/~jhayes/IMGS/cline.gif" ALIGN=CENTER></a><br><!WA1><IMG BORDER=2 ALT="John" ALIGN=right SRC="http://www.eecs.umich.edu/~jhayes/IMGS/mjhayes.gif" width=250 height=200" ></a><br><h1> JOHN P. HAYES </h1><h2> Professor of Electrical Engineering <br> and Computer Science </h2><br><address> EECS Bldg. Room 2114E, University of Michigan, <br>1301 Beal Avenue, Ann Arbor, MI 48109-2122, USA. <br>Telephone: (313) 763-0386 <br>Fax: (313) 763-4617 <br>E-mail: <!WA2><A HREF="mailto:jhayes@eecs.umich.edu">jhayes@eecs.umich.edu </A></address><br><!WA3><IMG BORDER=1 ALIGN=center SRC="http://www.eecs.umich.edu/~jhayes/IMGS/cline.gif" ALIGN=CENTER></a><center> <h2> BACKGROUND </h2> </center>John P. Hayes has been a Professor of <!WA4><A HREF="http://www.eecs.umich.edu/"> EECS </A> atthe <!WA5><A HREF="http://www.umich.edu"> University of Michigan </A> since1982. Prior to that, he was on the faculty of the University of SouthernCalifornia, Los Angeles. He teaches and conducts research in the areas ofcomputer-aided design and testing of digital systems, computer architecture,VLSI design, and fault-tolerant computing. He was the founding director ofMichigan's <!WA6><A HREF="http://www.eecs.umich.edu/acal"> Advanced Computer Architecture Laboratory </A>.Prof. Hayes is the authorof five books including Computer Architecture and Organization, (McGraw-Hill,2nd ed. 1988), Layout Minimization for CMOS Cells, (Kluwer, 1992), andIntroduction to Digital Logic Design, (Addison-Wesley, 1993), as well asnumerous technical papers. He received the B.E. degree from the NationalUniversity of Ireland, Dublin and his M.S. and Ph.D. degrees from theUniversity of Illinois, Urbana-Champaign. Prof. Hayes is a Fellow of IEEE, and amember of ACM and Sigma Xi.<!WA7><IMG BORDER=1 SRC="http://www.eecs.umich.edu/~jhayes/IMGS/cline.gif" ALIGN=CENTER></a><center> <h2> CURRENT RESEARCH </h2> </center>Our group is currently conducting research on the following topics:Hierarchical testing of digital circuits; Built-in self-test (BIST); Designverification; Fault-tolerant architectures for safety-critical applications;Design with field-programmable gates arrays (FPGAs); Automated layout methodsfor CMOS cells; and High-level timing analysis. The research is sponsoredby DARPA, NSF, and various industrial organizations.For further information, see the list of recent publications below.Also see the DARPA-sponsored project on <!WA8><A HREF="http://www.eecs.umich.edu/VERIFY/"> hardware design verification for microprocessors </A>. <!WA9><IMG BORDER=1 SRC="http://www.eecs.umich.edu/~jhayes/IMGS/cline.gif" ALIGN=CENTER></a><center> <h2> RECENT PUBLICATIONS </h2> </center><ol><li> H.-K. Ku and J. P. Hayes, "Structural fault tolerance in VLSI-based systems,"<em> Proc. 4th Great Lakes Symp. on VLSI</em>, Notre Dame, Ind., pp. 50-55, March 1994.<li> M. J. Batek and J. P. Hayes, "Optimal testing and design of adders," <em> VLSIDesign, (Special Issue on Digital Hardware Testing)</em>, vol. 1, no. 4, pp. 285-298,1994. <li> H.-K. Ku and J. P. Hayes, "Connectivity and fault tolerance of multiple-bussystems," <em> Proc. 24th Fault-Tolerant Computing Symp.</em>, Austin, Tex., pp. 372-381,June 1994. <li> K. Chakrabarty and J. P. Hayes, "Efficient test response compression formultiple-output circuits," <em> Proc. Int'l Test Conf.</em>, Washington, D.C., pp.501-510, Oct. 1994. <li> K. Chakrabarty and J. P. Hayes, "Cumulative balance testing of logic circuits,"<em> IEEE Trans. on VLSI Systems</em>, vol. 3, pp. 72-83, March 1995.<li> M. C. Hansen and J. P. Hayes, "High-level test generation usingphysically-induced faults," <em> Proc. 13th VLSI Test Symp.</em>, Princeton, N.J., pp.20-28, May 1995. <li> M. C. Hansen and J. P. Hayes, "High-level test generation using symbolicscheduling," <em> Proc. Int'l Test Conf.</em>, Washington, D.C., pp. 586-595, Oct. 1995.<li> K. Chakrabarty, B. T. Murray and J. P. Hayes, "Optimal space compaction of testresponses," <em> Proc. Int'l Test Conf.</em>, Washington, D.C., pp. 834-843, Oct. 1995.<li> A. Chowdhary and J. P. Hayes, "Technology mapping for field-programmable gatearrays using integer programming," <em> Proc. Int'l Conf. on Computer-Aided Design(ICCAD 95)</em>, San Jose, Calif., pp. 346-352, Nov. 1995. <li> H. Al-Asaad and J. P. Hayes, "Design verification via simulation and automatictest pattern generation," <em> Proc. Int'l Conf. on Computer-Aided Design(ICCAD 95)</em>, San Jose, Calif., pp. 174-180, Nov. 1995. <li> H. Yalcin and J. P. Hayes, "Hierarchical timing analysis using conditionaldelays," <em> Proc. Int'l Conf. on Computer-Aided Design (ICCAD 95)</em>, San Jose,Calif., pp. 371-377, Nov. 1995. <li> F. Harary and J. P. Hayes, "Node fault tolerance in graphs," <em> Networks</em>, vol. 27, pp. 19-23, 1996. <li> K. Chakrabarty and J. P. Hayes, "Balance testing and balance-testable designof logic circuits," <em> Journal of Electronic Testing</em>,vol. 8, pp. 71-86, 1996.<li> R. D. Blanton and J. P. Hayes, "Testability of convergent tree circuits," <em> IEEETrans. on Computers</em>, vol. 45, pp. 950-963, Aug. 1996. <li> A. Gupta, S.-C. The, and J. P. Hayes, "XPRESS: A Cell Layout Generator with Integrated Transistor Folding," <em>Proc. European Design & Test Conf. </em>, Paris, pp.393-400, March 1996.<li> R. D. Blanton and J. P. Hayes, "Design of a fast, easilytestable ALU," <em> Proc. 14th VLSI Test Symp.</em>,Princeton, NJ, pp. 9-16, April 1996.</ol><!WA10><IMG BORDER=1 SRC="http://www.eecs.umich.edu/~jhayes/IMGS/cline.gif" ALIGN=CENTER></a><center> <h2> CURRENT GRADUATE STUDENTS </h2> </center><DD> <!WA11><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA12><A HREF="http://www.eecs.umich.edu/~pagarwal"> Parul Agarwal</A> (pagarwal@eecs.umich.edu)<DD> <!WA13><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA14><A HREF="http://www.eecs.umich.edu/~halasaad"> Hussain Al-Asaad</A> (halasaad@eecs.umich.edu)<DD> <!WA15><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA16><A HREF="http://www.eecs.umich.edu/~amitc"> Amit Chowdhary</A> (amitc@eecs.umich.edu)<DD> <!WA17><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA18><A HREF="http://www.eecs.umich.edu/~avigupta"> Avaneendra Gupta</A> (avigupta@eecs.umich.edu)<DD> <!WA19><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA20><A HREF="http://www.eecs.umich.edu/~hyungwon"> Hyungwon Kim</A> (hyungwon@eecs.umich.edu)<DD> <!WA21><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA22><A HREF="http://www.eecs.umich.edu/~hakan"> Hakan Yalcin</A> (hakan@eecs.umich.edu)<br><!WA23><IMG BORDER=1 SRC="http://www.eecs.umich.edu/~jhayes/IMGS/cline.gif" ALIGN=CENTER></a><center> <h2> RECENTLY GRADUATED Ph.D. STUDENTS </h2> </center><DD> <!WA24><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA25><A HREF="http://www.eecs.umich.edu/~lauren"> Brian T. Murray </A>(bmurray@predator.cs.gmr.com)<DD> Graduated 1994. Thesis title: "Hierarchical testing using precomputed tests for modules." <DD> Current position: General Motors Research Labs., Warren, MI.<DD> <!WA26><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA27><A HREF="http://www.ece.cmu.edu/afs/ece/usr/blanton/professional.home.html"> Ronald D. (Shawn) Blanton </A> (blanton@ece.cmu.edu)<DD> Graduated 1995. Thesis title: "Design and testing of regular circuits."<DD> Current position: Assistant Professor of ECE, Carnegie-Mellon University, Pittsburgh, PA.<DD> <!WA28><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA29><A HREF="http://www.eecs.umich.edu/~hungkuei"> Hung-Kuei Ku </A>(hkku@mink.mt.att.com) <DD> Graduated 1995. Thesis title: "Fault-tolerant interconnection networks for multiprocessors." <DD> Current position: AT&T Bell Laboratories, Middletown, NJ.<DD> <!WA30><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA31><A HREF="http://www.eecs.umich.edu/~krish"> Krishnendu Chakrabarty </A> (kchakrab@bu.edu)<DD> Graduated 1995. Thesis title: "Test response compaction for built-in self testing."<DD> Current position: Assistant Professor of EE, Boston University, Boston, MA.<DD> <!WA32><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA33><A HREF="http://www.eecs.umich.edu/~cheezer"> Michael J. Batek </A>(cheezer@caen.engin.umich.edu)<DD> Graduated 1995. Thesis title: "Test-driven transformations in logic design." <DD> Current position: MicroUnity Systems Engineering, Sunnyvale, CA.<DD> <!WA34><IMG SRC="http://www.eecs.umich.edu/~jhayes/IMGS/ball_pink_icon.gif"> <!WA35><A HREF="http://www.eecs.umich.edu/~mhansen"> Mark C. Hansen </A>(c22mch@icdc.delcoelect.com) <DD> Graduated 1996. Thesis title: "Symbolic functional test generation with guaranteed low-level fault detection." <DD> Current position: Delco Electronics, Kokomo, Ind.</DL><!WA36><IMG BORDER=1 SRC="http://www.eecs.umich.edu/~jhayes/IMGS/cline.gif" ALIGN=CENTER></a></body></html>⌨️ 快捷键说明
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