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<HTML><HEAD><TITLE>Joy Shetler's Home Page</TITLE><BASE HREF="http://phoenix.csc.calpoly.edu/"></HEAD><BODY bgcolor="#FFFFFF"><!-- The following is an interlaced gif --><!WA0><IMG ALIGN = left BORDER = 0 hspace = 20 height = 110 width = 90 SRC = "http://phoenix.csc.calpoly.edu/joy2.gif" ALT = "department issue photograph" ><!WA1><IMG SRC=http://phoenix.csc.calpoly.edu/shetler.jpg ALT="[Photo]" ALIGN=LEFT HSPACE=10 VSPACE=10><BR><! Put your own vital stats in the appropriate places below. ><P>This homepage is currently under development and revision. Forclarification, please send e-mail to the address given at the bottom of this page.<H1>Joy Shetler</H1><EM>Associate Professor<Br>Computer Engineering Program<Br>B.S., Electronic Engineering (Honors), Cal Poly, San Luis Obispo<Br>M.S., Ph.D., Electrical And Computer Engineering, UC Santa Barbara <P>Office: 20-213<Br>Phone: 805/756-2309<Br>Email: <!WA2><A HREF="mailto:jshetler@phoenix.csc.calpoly.edu">jshetler@phoenix.csc.calpoly.edu </A></EM><HR><P><H4>Biography:</H4>Professor Shetler's research interests are in computer architecture and design.In June 1996, she received a CAREER grant from the National ScienceFoundation to establish an active research effort in microelectronic systems architecture that enhances the undergraduate curriculum in Computer Engineering,Computer Science and Electrical Engineering, and introduces students to new computer architectures, new technology and microelectronic systems.<P>The ideas developed by this research will be incorporated into the microprocessor and computer architecture curriculum. The focus of the researchcomponent is to devise and test Instruction Level Parallelism (ILP)techniques and mechanisms. Programmable Logic Devices, such as FPGAs, areused to implement rapid system prototyping of custom computer designs andare also used to implement custom components in reconfigurable architectures.Part of this project involves developing a rapid-prototyping platform.<P>Her industrial experience includes computer designat Burroughs Corp. (now UNISYS) for four years and at Trilogy Systems ofCupertino (now defunct). At Burroughs, she was a designer of the A9/A10mainframe. While at Trilogy, she designed a multiprocessor cache coherencymechanism using Wafer Scale Integration (WSI).<H4>Compcon</H4><P><DL>Dr. Shetler is currently serving on the steering committee for <DD><!WA3><AHREF="http://www.compcon.org">Compcon 97.</A> <DT></DL><H4>Teaching Areas:</H4><P>Dr. Shetler is teaching CPE 316 and CPE X436 for Fall Quarter, 1996. Onlythe information for those courses is valid. Information on other coursesshe has taught may not be up to date.<! replace nnn's with proper course number, title, and description, etc ><DL> <DT> Digital Logic Design <DD><!WA4><A HREF=http://phoenix.csc.calpoly.edu/~jshetler/CPE219.html>CPE 219</A> <p> This course covers introductory material on digital design techniques and theory.</DL><DL> <DT> Computer Architecture II <DD><!WA5><A HREF=http://phoenix.csc.calpoly.edu/~jshetler/CPE315.html>CPE 315</A> <p> This course covers computer architecture and microprogramming. The emphasis is on the RTL (Register Transfer Level) design of RISC and CISC based architectures.</DL><DL> <DT> Computer Architecture III <DD><!WA6><A HREF=http://phoenix.csc.calpoly.edu/~jshetler/CPE316.html>CPE 316</A> <p> This course covers computer architecture and interfacing techniques. The emphasis is on interfacing at the system bus level using asynchronous and synchronous protocols. Memory addressing strategies and memory mapped I/O are also covered. The lab associated with this course covers several team projects.</DL><DL> <DT> Digital Systems Design <DD><!WA7><A HREF=http://phoenix.csc.calpoly.edu/~jshetler/CPE319.html>CPE 319</A> <p> This course covers the design of digital systems using combinational and sequential circuits. The course covers current implementation strategies including the use of PLDs and FPGAs.</DL><DL> <DT> Microprocessor Systems Design <DD><!WA8><A HREF=http://phoenix.csc.calpoly.edu/~jshetler/CPEX436.html>CPE X436</A> <p> This course covers microprocessor systems design.</DL><H4>Research Interests:</H4><DL> <DT> multithreaded processor designs <DD> description <DT> FPGA implementations <DD>description <DD>and more description</DL><H4>Recent & Current Master Theses students:</H4><UL> <LI>Reggie Hunt - June 1996 - The Design and Implementation of An Object-Based, Interrupt Driven Operating System <LI>Mike Griffin - June 1996 - The Design and Implementation of An Object-Based, Interrupt Driven Operating System <LI>Jeff Bain - June 1996 - Design and Analysis of Instruction Issue Logic <LI>Ed Stoebner - In progress <LI>Chia Yang - In progress</UL><H4>Recent Senior Projects Completed:</H4><UL> <LI>Dale Wills - June 1995 - Automobile Racetrack Display using an MC68HC11 <LI>Heidi Rylance - December 1995 - Implementation of the PowerPC's Instruction Queue Using Schematic Capture and FPGAs <LI>Brandon Blodget - December 1995 - Implementation of the PowerPC's Instruction Queue Using Schematic Capture and FPGAs <LI>Charles DeCraene - March 1996 - MC68000 Based Small Computer</UL><H4>Senior Projects in Progress:</H4>Please note that these are preliminary topics and may change slightly!<UL> <LI>Alison Barnes - Robot Controller board using an embedded microprocessor <LI>Kai Lee - Microprocessor Systems Development using Wind River Systems Software <LI>Phong Nguyen - VHDL implementation of a co-processor using FPGAs <LI>Carlos Rios - PCI based application</UL><H4>Accelerators:</H4><UL><LI> include pointers here to things of interest, etc.<LI></UL><DL> <DT></DL><HR><ADDRESS> <LI>Please send any constructive comments to<!WA9><AHREF="mailto:jshetler@phoenix.csc.calpoly.edu"> Joy Shetler</A><LI>copyRight © 1996 by CSC dept Cal Poly. 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