http:^^www.cs.wisc.edu^~markhill^markhill.html

This data set contains WWW-pages collected from computer science departments of various universities

Performance Implications of Tolerating Cache Faults,
</cite></A>
Andreas Farid Pour and Mark D. Hill,
IEEE Transactions on Computers (TOC), March 1993.

<P>
<!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><!WA58><A HREF="ftp://ftp.cs.wisc.edu/wwt/isca93_mechanisms.ps">
<cite>
Mechanisms for Cooperative Shared Memory,
</cite>
</A>
David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus,
Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla,
Steven K. Reinhardt,
International Symposium on Computer Architecture (ISCA), May 1993.
<P>
<!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><!WA59><A HREF="ftp://ftp.cs.wisc.edu//wwt/sigmetrics93_wwt.ps"><cite>
The Wisconsin Wind Tunnel:  Virtual Prototyping of Parallel Computers,
</cite></A>
Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck,
James C. Lewis, David A. Wood,
ACM SIGMETRICS, May 1993.

<h3>1992</h3>

<P>
<!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><!WA60><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/tocs92_coloring.ps"><cite>
Page Placement Algorithms for Large Real-Index Caches,
</cite></A>
R. E. Kessler, Mark D. Hill,
ACM Transactions on Computer Systems, November 1992.

<P>
<!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><!WA61><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/jpdc92_plpc.ps"><cite>
Programming for Different Memory Consistency Models,
</cite></A>
Kourosh Gharachorloo, Sarita V. Adve, Anoop Gupta,
John L. Hennessy, Mark D. Hill,
Journal of Parallel and Distributed Computing, August 1992.

<P>
<!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><!WA62><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/isca92_twopages.ps"><cite>
Tradeoffs in Supporting Two Page Sizes,
</cite></A>
Madhusudhan Talluri, Shing Kong, Mark D. Hill, David A. Patterson,
International Symposium on Computer Architecture (ISCA), May 1992.

<h3>1991</h3>

<P>
<!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><!WA63><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/isca91_race_detection.ps"><cite>
Detecting Data Races on Weak Memory Systems,
</cite></A>
Sarita V. Adve, Mark D. Hill, Barton P. Miller, Robert H. B. Netzer,
International Symposium on Computer Architecture (ISCA), June 1991.

<P>
<!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><!WA64><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/isca91_coherence.ps"><cite>
Comparison of Hardware and Software Cache Coherence Schemes,
</cite></A>
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary K. Vernon,
International Symposium on Computer Architecture (ISCA), June 1991.

<P>
<!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><!WA65><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/sigmetrics91_renewal.ps"><cite>
A Model for Estimating Trace-Sample Miss Ratios,
</cite></A>
David A. Wood, Mark D. Hill, R. E. Kessler
ACM SIGMETRICS, May 1991.

<P>
<!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><!WA66><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/sigmetrics91_fully_assoc.ps"><cite>
Implementing Stack Simulation for Highly-Associative Memories (extended abstract)</cite></A>
Yul H. Kim,  Mark D. Hill, David A. Wood,
ACM SIGMETRICS, May 1991.

<h3>1990</h3>

<P>
<!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><!WA67><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/icpp90_seqcon.ps"><cite>
Implementing Sequential Consistency In Cache-Based Systems,
</cite></A>
Sarita V. Adve, Mark D. Hill,
International Conference on Parallel Processing, August 1990.

<P>
<!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><!WA68><A HREF="ftp://ftp.cs.wisc.edu/markhill/Papers/isca90_drf0.ps"><cite>
Weak Ordering - A New Definition,</cite></A>
Sarita V. Adve,  Mark D. Hill,
International Symposium on Computer Architecture (ISCA), June 1990.

<P>

<hr>

<h2><A NAME="theses">Ph.D. Graduates</A></h2>

<p>
<!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><!WA69><A HREF="http://www.cs.wisc.edu/~talluri/talluri.html"><strong>
Madhusudhan Talluri,
</strong></A>
Ph.D. Expected August 1995,
<!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><!WA70><A HREF="ftp://ftp.cs.wisc.edu/markhill/Theses/madhu_talluri.ps"><cite>
Use of Superpages and Subblocking in the Address Translation Hierarchy,
</cite></A>
first employment: Sun Microsystems,
current email: [e-mail].

<p>
<!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><!WA71><A HREF="http://www-ece.rice.edu/ece/faculty/Adve/sarita.html"><strong>
Sarita V. Adve,
</strong></A>
Ph.D. November 1993,
<!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><!WA72><A HREF="ftp://ftp.cs.wisc.edu/markhill/Theses/sarita_adve.ps"><cite>
Designing Memory Consistency Models for Shared-Memory Multiprocessors,
</cite></A>
first employment: Assistant Professor at Rice University,
current email: [e-mail].

<p>
<!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><!WA73><A HREF="http://www.cs.wisc.edu/cgi-bin/finger?kessler"><strong>
Richard E. Kessler,
</strong></A>
Ph.D. July 1991,
<!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><!WA74><A HREF="ftp://ftp.cs.wisc.edu/markhill/Theses/richard_kessler_body.ps"><cite>
Analysis of Multi-Megabyte Secondary CPU Cache Memories   
</cite></A>
<!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><!WA75><A HREF="ftp://ftp.cs.wisc.edu/markhill/Theses/richard_kessler_toc.ps">(click here for table of contents),</A>
first employment: Cray Research,
current email: [e-mail].

<p>
<hr>
<address>Last Updated
Wed Aug 14 16:52:16 CDT 1996
</address>
<p>
Keywords to help search engines rank this page higher than my other pages:
Mark Hill Home Page, Computer Sciences, Wisconsin.
Mark Hill Home Page, Computer Sciences, Wisconsin.
Mark Hill Home Page, Computer Sciences, Wisconsin.
Mark Hill Home Page, Computer Sciences, Wisconsin.
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