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Date: Thu, 07 Nov 1996 19:07:50 GMTServer: NCSA/1.5Content-type: text/htmlLast-modified: Fri, 05 Apr 1996 17:01:30 GMTContent-length: 9991<html><head><title> Guri Sohi's Home Page </title></head><body><hr><!-- This is an example comment so I remember how to do it. --><h1> Gurindar S. Sohi </A> (<!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><A HREF="http://www.cs.wisc.edu/cgi-bin/finger?sohi">sohi@cs.wisc.edu)</A> </h1><base href="http://www.cs.wisc.edu/~sohi/"><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><IMG SRC="http://www.cs.wisc.edu/~sohi/sohi.gif"><br>Associate Professor of <!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href="http://www.cs.wisc.edu/">Computer Sciences </a><br> and<!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href="gopher://sunserv0.cae.wisc.edu/11/ece">Electrical and Computer Engineering</a><p><ul><li> <!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><A HREF="#addresses">Addresses</A><li> <!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><A HREF="#education">Education</A><li> <!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><A HREF="#research">Research Interests and Summary</A><li> <!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><A HREF="#students">Current Graduate Students</A><li> <!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><A HREF="#talks">Recent Talks</A><li> <!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><A HREF="#sampler"> Recent Publications</A><li> <!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><A HREF="#phdgrads"> Recent Ph.D Graduates</A></ul><hr><h3><A NAME="addresses">Addresses:</A></h3>Department of Computer Sciences<br>University of Wisconsin - Madison<br>1210 West Dayton Street<br>Madison, WI 53706 USA<br><br>sohi@cs.wisc.edu<br>Phone: 608-262-7985<br>Departmental Office: 608-262-1204<br>Fax: 608-262-9777<p><h3><A NAME="education">Education:</A></h3><ul><li> Ph.D. (Computer Science) University of Illinois - Urbana, 1985<li> M.S. (Electical Engineering) University of Illinois - Urbana, 1983<li> B.E. (Electrical and Electronics Engineering) Birla Institute of Technology and Science - Pilani, India, 1981</ul><h3><A NAME="research">Research Interests:</A></h3><ul><li> Instruction-level parallel (ILP) processing<li> Compiling for ILP architectures<li> Shared memory multiprocessors<li> Memory Systems</ul><p><hr><h2> Research Summary </h2> <ul>My current research focuses on the design of thehighest performance uniprocessors of a current generation.Currently we are investigating the architecture ofa circa 2000 processor. With plenty of transistors availableon a chip, the challenge is to use these resources to getthe highest possible performance when executing a sequential program.A target that we have set for ourselves is to sustain the execution ofover 10 instructions per cycle,for ordinary non-numeric application programs.<P>My research group is investigating several issues that needto be resolved before our goals can be achieved.We are studying and characterizing thenature of instruction-level parallelism in non-numericapplication programs in order to understand the available parallelism andhow it could be exploited.The bulk of my group's research effort is expended in continuing thedevelopment of the<!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><a href="http://www.cs.wisc.edu/~mscalar"> <em>Multiscalar</em> </a> processing model,a novel paradigm for exploiting ILP.Currently we are developing the Multiscalar compiler, andcarrying out detailed simulation studies to assessthe potential of the Multiscalar concept.</ul><hr><h2><A NAME="students">Current Graduate Students</A></h2><ul><li> <!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><a href="http://www.cs.wisc.edu/~austin/austin.html">Todd Austin</a><li> <!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><a href="http://www.cs.wisc.edu/~breach/breach.html">Scott Breach</a><li> <!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><a href="http://www.cs.wisc.edu/~moshovos/moshovos.html">Andreas Moshovos</a><li> <!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><a href="http://www.cs.wisc.edu/~vijay/vijay.html">T.N. Vijaykumar</a></ul><hr><h2><A NAME="talks">Recent Talks</A></h2><ul><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><A HREF="ftp://ftp.cs.wisc.edu/sohi/talks/ibm.nov95.ps.Z"><cite>Will Instruction Sets be Important in Future Processors?</A>given at the RISC in 1995 Symposium held at IBM T. J. Watson ResearchCenter, Yorktown Heights, NY, November 7-8, 1995.File is compressed postscript, generated by Framemaker.<P><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><A HREF="ftp://ftp.cs.wisc.edu/sohi/talks/intel.oct95.ps.Z"><cite>Multiscalar Processors.</A>The generic Multiscalar talk, given at several places.File is compressed postscript, generated by Framemaker.</ul><hr><hr><h2><A NAME="sampler">Recent Publications</A></h2><ul><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca96.HBAT.ps.Z"><cite>High-Bandwidth Address Translation for Multiple-Issue Processors</i></a>,</A>T. M. Austin and G. S. Sohi, to appear in23rd Annual International Symposium on Computer Architecture, May 1996.An appendix of<!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><a href="ftp://ftp.cs.wisc.edu/sohi/isca96-results.ps.Z">detailed results</a>is also available.)<br><P><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><A HREF="ftp://ftp.cs.wisc.edu/sohi/micro28.zcl.ps.Z"><cite>Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency</A>T. M. Austin and G. S. Sohi,28th Annual International Symposium on Microarchitecture (MICRO-28), 1995.<P><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><A HREF="ftp://ftp.cs.wisc.edu/sohi/super.proc.ps.Z"><cite>The Microarchitecture of Superscalar Processors</A>J. E. Smith and G. S. Sohi,in Proceedings of the IEEE, December 1995.<P><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><A HREF="ftp://ftp.cs.wisc.edu/sohi/arb.ps.Z"><cite>A Hardware Mechanism for Dynamic Reordering of Memory References</cite></A>M. Franklin and G. S. Sohi,to appear in IEEE Transactions on Computers.<P><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca95.multiscalar.ps.Z"><cite>Multiscalar Processors,</cite></A>G. S. Sohi, S. Breach, and T. N. Vijaykumar,22th International Symposium on Computer Architecture, 1995.<P><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca95.fast.ps.Z"><cite>Streamlining Data Cache Access with Fast Address Calculation,</cite></A>T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi,22th International Symposium on Computer Architecture, 1995.<P><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><A HREF="ftp://ftp.cs.wisc.edu/sohi/micro27.ps.Z"><cite>The Anatomy of the Register File in a Multiscalar Processor,</cite></A>S. Breach, T. N. Vijaykumar, and G. S. Sohi,27th Annual International Symposium on Microarchitecture (MICRO-27), 1994.<P><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><A HREF="ftp://ftp.cs.wisc.edu/sohi/tpdc94.combine.ps.Z"><cite>Request Combining in Multiprocessors with Arbitrary Interconnection Networks, </cite></A>A. Lebeck and G. S. Sohi, in IEEE Transactions on Parallel and Distributed Systems, 1994.<P><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><A HREF="ftp://ftp.cs.wisc.edu/sohi/safe-c.PLDI94.ps.Z"><cite>Efficient Detection of All Pointer and Array Access Errors, </cite></A>T. M. Austin, S. E. Breach and G. S. Sohi,SIGPLAN '94 Conference on Programming Language Design and Implementation, 1994.<P><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca94.ps.Z"><cite>Guarded Execution and Branch Prediction in Dynamic ILP Processors, </cite></A>D. Pnevmatikatos and G. S. Sohi, 21th International Symposium on Computer Architecture, 1994.<P><cite>Memory Systems,</cite>J. R. Goodman and G. S. Sohi, The Handbook of Electrical Engineering, CRC Press, 1993.<P><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><A HREF="ftp://ftp.cs.wisc.edu/sohi/micro26.ps.Z"><cite>Control Flow Prediction for Dynamic ILP Processors, </cite></A>D. Pnevmatikatos, M. Franklin and G. S. Sohi,26th Annual International Symposium on Microarchitecture (MICRO-26), 1993.<P><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><!WA30><A HREF="ftp://ftp.cs.wisc.edu/sohi/micro25.ps.Z"><cite>Register Traffic Analysis for Streamlining Inter-operation Communicationin Fine-Grain Parallel Processors,</cite></A>M. Franklin and G. S. Sohi, 25th Annual International Symposium on Microarchitecture(MICRO-25), 1992.<P><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><!WA31><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca92.esw.ps.Z"><cite>The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism,</cite></A>M. Franklin and G. S. Sohi, 19th International Symposium on Computer Architecture, 1992.<P><!WA32><!WA32><!WA32><!WA32><!WA32><!WA32><!WA32><!WA32><!WA32><!WA32><!WA32><!WA32><!WA32><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca92.ilp.ps.Z"><cite>Dynamic Dependency Analysis of Ordinary Programs,</cite></A>T.M. Austin and G. S. Sohi, 19th International Symposium on Computer Architecture, 1992.<P><!WA33><!WA33><!WA33><!WA33><!WA33><!WA33><!WA33><!WA33><!WA33><!WA33><!WA33><!WA33><!WA33><A HREF="ftp://ftp.cs.wisc.edu/tech-reports/reports/93/tr1197.ps.Z"><cite>Efficient Detection of All Pointer and Array Access Errors</cite></A>T.M. Austin, S. E. Breach and G. S. Sohi,Technical Report #1197, Computer Sciences Department, University of Wisconsin-Madison, December 1993.<P><!WA34><!WA34><!WA34><!WA34><!WA34><!WA34><!WA34><!WA34><!WA34><!WA34><!WA34><!WA34><!WA34><A HREF="ftp://ftp.cs.wisc.edu/tech-reports/reports/93/tr1193.ps.Z"><cite>Guarded Execution and Branch Prediction in Dynamic ILP Processors</cite></A>D. N. Pnevmatikatos and G. S. Sohi,Technical Report #1193, Computer Sciences Department, University of Wisconsin-Madison, November 1993.<P><!WA35><!WA35><!WA35><!WA35><!WA35><!WA35><!WA35><!WA35><!WA35><!WA35><!WA35><!WA35><!WA35><A HREF="ftp://ftp.cs.wisc.edu/tech-reports/reports/93/tr1189.ps.Z"><cite>Knapsack: A Zero-Cycle Memory Hierarchy Component</cite></A>T. M. Austin, T. N. Vijaykumar, and G. S. Sohi,Technical Report #1189, Computer Sciences Department, University of Wisconsin-Madison, November 1993.<P><!WA36><!WA36><!WA36><!WA36><!WA36><!WA36><!WA36><!WA36><!WA36><!WA36><!WA36><!WA36><!WA36><A HREF="ftp://ftp.cs.wisc.edu/tech-reports/reports/93/tr1162.ps.Z"><cite>Tetra: Evaluation of Serial Program Performance on Fine-Grain Parallel Processors</cite></A>T. M. Austin and G. S. Sohi,Technical Report #1162, Computer Sciences Department, University of Wisconsin-Madison, July 1993.</ul><hr><h2><A NAME="phdgrads">Recent Ph.D Grads</A></h2><ul><P><em>Todd Austin,</em></A>Ph.D., April 1996,<!WA37><!WA37><!WA37><!WA37><!WA37><!WA37><!WA37><!WA37><!WA37><!WA37><!WA37><!WA37><!WA37><A HREF="ftp://ftp.cs.wisc.edu/sohi/austin.thesis.ps.Z"><cite>Hardware and Software Mechanisms for Reducing Load Latency</cite></A><P><em>Dionisios Pnevmatikatos,</em></A>Ph.D., December 1995,<!WA38><!WA38><!WA38><!WA38><!WA38><!WA38><!WA38><!WA38><!WA38><!WA38><!WA38><!WA38><!WA38><A HREF="ftp://ftp.cs.wisc.edu/sohi/pnevmati.thesis.ps.Z"><cite>Incorporating Guarded Execution into Existing Instruction Sets</cite></A><P><em>Manoj Franklin,</em></A>Ph.D., December 1993,<!WA39><!WA39><!WA39><!WA39><!WA39><!WA39><!WA39><!WA39><!WA39><!WA39><!WA39><!WA39><!WA39><A HREF="ftp://ftp.cs.wisc.edu/sohi/franklin.thesis.ps.Z"><cite>The Multiscalar Architecture</cite></A><P><em>Mark Friedman,</em>Ph.D., January 1992,<!WA40><!WA40><!WA40><!WA40><!WA40><!WA40><!WA40><!WA40><!WA40><!WA40><!WA40><!WA40><!WA40><A HREF="ftp://ftp.cs.wisc.edu/sohi/friedman.thesis.ps.Z"><cite>An Architectural Characterization of Prolog Execution</cite></A><P><em>Sriram Vajapeyam,</em>Ph.D., December 1991,<!WA41><!WA41><!WA41><!WA41><!WA41><!WA41><!WA41><!WA41><!WA41><!WA41><!WA41><!WA41><!WA41><A HREF="ftp://ftp.cs.wisc.edu/sohi/sriram.thesis.ps.Z"><cite>Instruction Level Characterization of the Cray Y-MP Processor</cite></A><P><em>Men-Chow Chiang,</em>Ph.D., September 1991,<!WA42><!WA42><!WA42><!WA42><!WA42><!WA42><!WA42><!WA42><!WA42><!WA42><!WA42><!WA42><!WA42><A HREF="ftp://ftp.cs.wisc.edu/sohi/chiang.thesis.ps.Z"><cite>Memory System Design for Bus Based Multiprocessors</cite></A></ul><hr><address> Last Updated: 5 April 1996 </address><hr></body></html>⌨️ 快捷键说明
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