http:^^www.cs.wisc.edu^~david^david.html

This data set contains WWW-pages collected from computer science departments of various universities

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<cite>Accuracy vs. Performance in Parallel Simulation of Interconnection Networks</cite></A>,<br>
Douglas C. Burger and David A. Wood.<br>
In the proceedings of the 9th International Parallel Processing Symposium, April, 1995.<br>

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<CITE>
Application-Specific Protocols for User-Level Shared Memory,
</CITE>
</A>
Babak Falsafi, Alvin Lebeck, Steven Reinhardt, Ioannis Schoinas,
Mark Hill, James Larus, Anne Rogers, and David Wood,
In Proceedings of Supercomputing '94.

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<CITE>
Fine-grain Access Control for Distributed Shared Memory,
</CITE>
</A>
Ioannis Schoinas, Babak Falsafi, Alvin Lebeck, Steven Reinhardt,
James Larus, and David Wood,
Proceedings of ASPLOS VI.

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<CITE>
Tempest and Typhoon: User-Level Shared Memory,
</CITE>
</A>
Steven Reinhardt, James Larus, and David Wood,
Proceedings of Int'l Symposium on Computer Architecture, 1994.

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<cite>
Cache Profiling and the SPEC Benchmarks: A Case Study,
</cite>
</A>
Alvin R. Lebeck and
David A. Wood,
pages 15-26,
IEEE COMPUTER,
October 1994

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<CITE>
Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors,
</CITE>
</A>
Mark D. Hill, James R. Larus, Steven K. Reinhardt, David A. Wood,
ACM Transactions on Computer Systems (TOCS), November 1993.

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<CITE>
The Wisconsin Wind Tunnel Project: An Annotated Bibliography,
</CITE>
</A>
Mark D. Hill, James R. Larus, David A. Wood,
Computer Architecture News, v. 22, n. 5, December 1994.
On-line version revised frequently.

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<CITE>
Wisconsin Architectural Research Tool Set (WARTS),
</CITE>
</A>
Mark D. Hill, James R. Larus, Alvin R. Lebeck, Madhusudhan Talluri,
David A. Wood,
Computer Architecture News (CAN), August 1993.
</UL>
<HR>

<hr>
<h2> Research Summary </h2> 

My main research goals lie in developing cost-effective computer
architectures that take advantage of rapidly changing technologies.  My
research program has two major thrusts:  
<ul>
<li> evaluating the performance,
feasibility, and correctness of new architectures, and
<li> developing new tools and techniques to facilitate this evaluation.
</ul>
Currently, this research focusses on the following three areas:
<ul>
<li> multi-paradigm multiprocessors,
which efficiently integrate shared-memory, message-passing, and hybrid
programming paradigms,
<li> a virtual prototyping system, which exploits the similarites
of an existing parallel machine to simulate a hypothetical parallel machine,
<li> and, techniques for understanding and tuning program performance.
</ul>

Recent results include developing a new interface---called
Tempest---between user-level protocol handlers and system-supplied
mechanisms. Tempest provides the mechanisms that allow programmers,
compilers, and program libraries to implement and use message passing,
transparent shared memory, and hybrid combinations of the two.  Tempest
mechanisms are low-overhead messages, bulk data transfer, virtual
memory management, and fine-grain access control.  The most novel
mechanism---fine-grain access control---allows user software to tag
blocks (e.g., 32 bytes) as read-write, read-only, or invalid, so the
local memory can be used to transparently cache remote data.<br><br>

We are exploring alternative ways to support this interface.
The first---called Typhoon---is
a proposed hardware
platform that implements the Tempest mechanisms with a fully-programmable,
user-level processor in the network interface.  A reverse-translation
table (RTLB) invokes the network processor when it detects a fine-grain
access fault.
We have simulated Typhoon on the Wisconsin Wind Tunnel and found that
a transparent shared-memory protocol running on Typhoon performs
comparably +/- 30% to an
all-hardware Dir{N}NB cache-coherence protocol for five shared-memory
programs.<br><br>

We have also developed a new memory system simulation method that
optimizes the common case---cache hits---significantly reducing
simulation time.
Fast-Cache tightly integrates reference generation and simulation by
providing the abstraction of tagged memory blocks: each reference
invokes a user-specified function depending upon the reference type and
memory block state. The simulator controls how references are processed
by manipulating memory block states, specifying a special NULL function
for no action cases.  Fast-Cache implements this abstraction by using
binary-rewriting to perform a table lookup before each memory
reference. On a SPARCStation 10, Fast-Cache simulation times are two to
three times faster than a conventional trace-driven simulator that
calls a procedure on each memory reference; simulation times are only
three to six times slower than the original, un-instrumented program.
We are also investigating using Fast-Cache's binary rewriting techniques
to support the Tempest interface on existing hardware platforms.

<hr>
<address> Last Updated: July 11, 1996 </address>
<hr>

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