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Date: Mon, 11 Nov 1996 02:14:25 GMTServer: NCSA/1.5Content-type: text/html<HTML><HEAD><TITLE>Saluja, Kewal K.</TITLE></HEAD><BODY BACKGROUND="/graphics/backgrounds/3.gif"><!-- fac profile --><CENTER><H5>College of Engineering<BR>University of Wisconsin - Madison</H5> <P><TABLE BORDER=7><TR><TD><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><A HREF="http://www.engr.wisc.edu/ece/"><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><IMG SRC="http://www.engr.wisc.edu/ece/pics/eceicon.gif" WIDTH=75 HEIGHT=75 BORDER=0 ALT="ECE"></A></TD><TD WIDTH=400 ALIGN="center"><H2>Kewal K. Saluja</H2></TD></TR></TABLE></CENTER><P><TABLE><TR><TD VALIGN="top" WIDTH=200><TABLE BORDER=7><TR><TD><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><A HREF="http://www.engr.wisc.edu/ece/faculty/pics/saluja_kewal.jpg"><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><IMG SRC="http://www.engr.wisc.edu/ece/faculty/pics/saluja_kewal.gif" WIDTH=150 HEIGHT=200 BORDER=0 ALT="Kewal K. Saluja"></A></TD></TR></TABLE></TD><TD VALIGN="top"><H3>Professor</H3>4611 Engineering Hall<BR>1415 Engineering Drive<BR>Madison, WI 53706<BR>Tel: 608-262-6490
<BR>Fax: <BR><P>E-mail: <!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><A HREF="mailto:saluja@engr.wisc.edu
">saluja@engr.wisc.edu
</A><BR>Portrait: <!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><A HREF="http://www.engr.wisc.edu/ece/faculty/pics/saluja_kewal.jpg">   9K JPG</A><BR></TD></TR></TABLE><HR SIZE=3><DL><DT><B>Departments</B><DD><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><A HREF="http://www.engr.wisc.edu/ece/">Electrical and Computer Engineering</A><DD><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><A HREF="http://www.cs.wisc.edu/">Computer Science</A> <P><DT><B>Education</B>  <DD>PhD 1973, University of Iowa <P><DT><B>Research Interests</B><DD>design for testability, computer architecture, data compression, integrated circuits (VLSI), fault-tolerant computing <P></DL><HR SIZE=3>My general area of research interest is test generation and testableand reliable design of digital systems. To carry out research in thisarea we make extensive use of VLSI CAD and analysis tools. Theresearch involves modeling of faults, designing digital circuits, testgeneration, design modification for enhancing testability, built-inself-testing designs, fabrication of circuits and test application. <P>We are investigating techniques to make the test generation andfault simulation process efficient for both combinational andsequential circuits. Data compression and compaction methodsapplicable in design for testability and built-in self-testenvironment are being investigated. <P>In the area of built-in self-test we are concentrating on regularstructures such as programmable logic arrays and RAMs. We areinvestigating self-test algorithms which can be implemented inhardware with little performance and area penalty. In another projectwe are investigating ways to use built-in self-test hardware to test asystem while it is performing its normal operation. The goal is thatthe system is tested continuously as it operates with little or noimpact on system performance. <P>Much of our work is performed using facilities of the VLSI digitalsystem laboratory. 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SIZE="-1">Last Modified: Friday, 03-May-96 16:26:43 CDT</FONT><BR><FONT SIZE="-1">This page is best viewed by browsers that support TABLES.</FONT><BR><FONT SIZE="-1"><B>All photographs &#169; 1996 College of Engineering.</B></FONT><BR><FONT SIZE="-1">Address comments to <!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><A HREF="http://www.engr.wisc.edu/cgi-bin/mailto-form?webmaster@engr.wisc.edu"><I>webmaster@engr.wisc.edu</I></A></FONT></TD></TR></TABLE><HR><FONT SIZE="-2"><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><A 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