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Date: Thursday, 21-Nov-96 23:39:52 GMT
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<TITLE>Maged Michael's URCS Home Page</TITLE>

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<!-- <H1>Maged Michael, URCS Grad Student</H1> -->
<H2>Maged Michael,  Ph.D. Student</H2>

<P>
<hr>

<H3> Journal and Conference Papers </H3>
<UL> 

<!"ftp://ftp.cs.rochester.edu/pub/u/michael/PODC96.ps.gz">

 <LI> G. Hunt, M. Michael, S. Parthasarathy, and M. Scott, <B>``An
	Efficient Algorithm for Priority Queue Heaps,''</B> Technical
	Report 560, Department of Computer Science, University of
	Rochester, December 1994. A revised version to appear in
	<I>Information Processing Letters</I> (<!WA2><A
	HREF="http://www.elsevier.nl:80/section/computer/416/ipl/ipl.htm"><B>IPL</B></A>). <!WA3><A
	HREF="ftp://ftp.cs.rochester.edu/pub/papers/systems/94.tr560.Efficient_algorithm_for_concurrent_priority_queue_heaps.ps.gz">
	postscript </A>.

 <LI> A. Nguyen, M. Michael, A. Sharma, and J. Torrellas, <B>``The
	Augmint Multiprocessor Simulation Toolkit for Intel x86
	Architectures,''</B> In <I>Proceedings of the 1996 IEEE
	International Conference on Computer Design</I> (<!WA4><A
	HREF="http://www.ee.princeton.edu/~wolf/iccd-96.html"><B>ICCD</B></A>),
	Austin, TX, October 1996.  <!WA5><A
	HREF="ftp://ftp.cs.rochester.edu/pub/u/michael/ICCD96.ps.gz">
	postscript</A>.

 <LI> M. Michael and M. Scott,<B>``Simple, Fast, and Practical
	Non-Blocking and Blocking Concurrent Queue
	Algorithms,''</B> In <I>Proceedings of the 15th ACM Symposium on
	Principles of Distributed Computing</I> (<!WA6><A
	HREF="http://www.cs.cornell.edu/Info/People/chandra/podc96/podc96.html"><B>PODC</B></A>),
	pp. 267-275, Philadelphia, PA, May 1996.  <!WA7><A
	HREF="http://www.cs.rochester.edu/u/michael/PODC96.html"> postscript</A>.

 <LI> M. Michael and M. Scott, <B>``Implementation of Atomic
	Primitives on Distributed Shared Memory Multiprocessors,''</B>
	In <I>Proceedings of the First IEEE International Symposium on
	High Performance Computer Architecture</I> (<!WA8><A
	HREF="http://www.ece.ncsu.edu/hpca3"><B>HPCA</B></A>),
	pp. 222-231, Raleigh, NC, January 1995. <!WA9><A
	HREF="ftp://ftp.cs.rochester.edu/pub/papers/systems/95.HPCA.Implementing_Atomic_Primitives.ps.gz">
	postscript</A>.

</UL>

<H3> Posters and Workshops </H3>
<UL> 

 <LI> A. Nguyen, M. Michael, A. Sharma, and J. Torrellas,
	<B>``Augmint: An Execution-driven Multiprocessor Simulation
	Toolkit for Intel x86 Architecture,''</B> Poster,
	<I>Supercomputing '96</I> (<!WA10><A
	HREF="http://scxy.tc.cornell.edu/sc96/"><B>SC'96</B></A>),
	Pittsburgh, PA, November 1996.

 <LI> M. Michael, B. Lim, A. Nanda, and M. Scott, <B>``Protocol
	Processors vs. Custom Hardware Coherence Adaptors for
	SMP-based CC-NUMA Multiprocessor Architectures,''</B> <I>Sixth
	International Workshop on Scalable Shared Memory
	Multiprocessors</I> (<!WA11><A
	HREF="http://www.dolphinics.com/ssm-workshop.html"><B>SSMM</B></A>),
	Cambridge, MA, October 1996.

 <LI> M. Scott, W. Li, S. Dwarkadas, L. Kontothanassis, G. Hunt,
        M. Michael, R. Stets, N. Hardavellas, W. Meira, A. Poulos,
        M. Cierniak, S. Parthasarathy, and M. Zaki,
        <B>``Implementation of Cashmere,''</B> <I>Sixth International
        Workshop on Scalable Shared Memory Multiprocessors</I> (<!WA12><A
        HREF="http://www.dolphinics.com/ssm-workshop.html"><B>SSMM</B></A>),
        Cambridge, MA, October 1996. <!WA13><A
        HREF="http://www.cs.rochester.edu/u/scott/cashmere/SSMM_96/talk.html">
        html</A>.

 <LI> M. Michael and M. Scott, <B>``Scalable Atomic Primitives for
	Distributed Shared Memory Multiprocessors,''</B> In
	<I>Proc. of the Fourth International Workshop on Scalable
	Shared Memory Multiprocessors</I> (<B>SSMM</B>), Chicago, IL,
	April 1994.  <!WA14><A
	HREF="ftp://ftp.cs.rochester.edu/pub/u/michael/WSSMM94.ps.gz">
	postscript</A>.

</UL>
<P>

<H3> Technical Reports and Submitted for Publication </H3>
<UL> 

 <LI> M. Michael and M. Scott, <B>``Concurrent Update on
	Multiprogrammed Shared Memory Multiprocessors,''</B> Technical
	Report 614, Dept. of Computer Science, Univ. of Rochester,
	April 1996.  <!WA15><A
	HREF="ftp://ftp.cs.rochester.edu/pub/papers/systems/96.tr614.Concurrent_update_on_multiprogrammed_shared_mem_multiprocessors.ps.gz">
	postscript</A>.

 <LI> M. Scott and M. Michael, <B>``The Topological Barrier: A
	Synchronization Abstraction for Regularly-Structured Parallel
	Applications,'</B>'</A> Technical Report 605, Dept. of
	Computer Science, Univ. of Rochester, January 1996.  <!WA16><A
	HREF="ftp://ftp.cs.rochester.edu/pub/papers/systems/96.tr605.Topological_barrier.ps.gz">
	postscript</A>.

 <LI> M. Michael and M. Scott, <B>``Correction of a Memory Management
	Method for Lock-Free Data Structures,''</B> Technical Report
	599, Dept. of Computer Science, Univ. of Rochester, December
	1995. <!WA17><A
	HREF="ftp://ftp.cs.rochester.edu/pub/papers/systems/95.tr599.Memory_management_for_lock-free_data_structures.ps.gz">
	postscript</A>.

 <LI> M. Michael and M. Scott, <B>``Fast Mutual Exclusion Even with
	Contention,''</B></A> Technical Report 460, Dept. of Computer
	Science, Univ. of Rochester, June 1993.  <!WA18><A
	HREF="ftp://ftp.cs.rochester.edu/pub/papers/systems/93.tr460.fast_mutual_exclusion_even_with_contention.ps.Z">
	postscript</A>.

</UL>


<H3> Research Interests </H3>
<UL>
<LI> Thesis topic: Atomic Update on Shared Memory Multiprocessors.
     Advisor <!WA19><A HREF="http://www.cs.rochester.edu/u/scott">
     Prof. Michael L. Scott</A>. 
<LI> Multiprocessor Simulation Tools.
<LI> Medium and Large-Scale Shared Memory Multiprocessor Design.
<LI> CC-NUMA Cache Coherence Protocols.
</UL>

<H3>Augmint</H3>
 <UL>
 <LI> <!WA20><A HREF="http://www.csrd.uiuc.edu/iacoma/augmint.html">
	Augmint </A> is a multiprocessor simulation toolkit for Intel
	x86 architectures.  It was developed in collaboration
	with Anthony-Trung Nguyen and Arun Sharma, while working as
	summer interns for Intel Corporation in the summer of 1995.
</UL>

<H3>Algorithms</H3>
<UL>
<LI> <!WA21><A HREF="http://www.cs.rochester.edu/u/michael/pseudocode/PODC96-pc.html"> Fast Non-Blocking and
     Lock-Based Concurrent Queue Algorithms</A>.
<LI> <!WA22><A HREF="http://www.cs.rochester.edu/u/michael/pseudocode/TR560-pc.html"> Multiple-Lock Concurrent
     Priority Heap Algorithm</A>.
<LI> <!WA23><A HREF="http://www.cs.rochester.edu/u/michael/pseudocode/TR460-pc.html"> Fast Mutual Exclusion Lock
     Algorithm</A>. 
</UL>

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