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Date: Tue, 26 Nov 1996 18:52:04 GMTServer: NCSA/1.5MIME-version: 1.0Content-type: text/htmlLast-modified: Tue, 19 Nov 1996 14:52:10 GMTContent-length: 4730<HTML><HEAD> <TITLE>CSE422 Computer System Design</TITLE></HEAD><BODY><H1><BR>CSE 442: Computer System Design</H1><HR><H3>Professor:</H3><BLOCKQUOTE><!WA0><A HREF="http://www.cse.nd.edu/faculty/henry.html">Dr. Engene W. Henry</A><BR>326 Cushing Hall<BR>phone: 1-6408<BR>email: <!WA1><A HREF="mailto:ewh@cse.nd.edu">ewh@cse.nd.edu</A><BR><H3>Teaching Assistants:</H3><BLOCKQUOTE>Cathy Xu<BR>email: <!WA2><A HREF="mailto:qxu@bach.helios.nd.edu">qxu@bach.helios.nd.edu</A></BLOCKQUOTE><H3>Lecture:</H3><BLOCKQUOTE>Tuesday, Thursday, 117 DeBartolo Hall, 11:00-12:15</BLOCKQUOTE><H3>Laboratory:</H3><BLOCKQUOTE>The CSE Design Automation Laboratory in Room 245 Cushing Hall,containing three Sun SPARC workstations will be used in this course. In addition, the workstations in the College of Engineering Computer Laboratorywill be used. Software is available for schematic capture, hardware descriptionlanguages, simulaiton, and realization with standard ICs and Xilinx FPGAs. A Xilinx FPGA demonstration circuit board will be loaned to each design group.<BR></BLOCKQUOTE><H3>Texts:</H3><BLOCKQUOTE>No Required textbooks. <BR>References: <BR>James R. Armstrong and F. Gail Gray, <I>Structured Logic Design with VHDL,</I>, Prentice-Hall, 1993.<BR>J. Bhasker, <I> A VHDL Primer</I>,Revised Edition, Prentice-Hall, 1995.<BR>J. Bhasker,<I> A VHDL Synthesis Primer,</I> Prentice-Hall, 1996.<BR>Jesse H. Jenkins,<I> Designing with FPGAs and CPLDs,</I> Prentice-Hall,1994.<BR>Pak K. Chan and Samiha Mourad, <I>Digital Design Using Field ProgrammableGate Arrays,</I>Prentice-Hall, 1994.<BR>Giovanni De Micheli,<I>Synthesis and Optimization of Digital Circuits,</I>McGraw-Hill, 1994<BR>Abramovici, Breuer and Friedman,<I> Digital Systems Testing and TestableDesign,</I> Computer Science Press, 1990.<BR>IEEE Standard 694-1985, <I>Microprocessor Assembly Language,</I> CS No.952, 1985.<BR>IEEE 695-1985, <I>Microprocessor Universal Format for Object Modules,</I>CS No.954.<BR>Herbert B. Michaelson, <I>How to Write and Publish Engineering Papers and Reports,</I> Third Edition, Oryx Press, Phoenix, AZ, 1990.<BR>John P. Hayes, <I>Introduction to Digital Logic Design,</I> Addison-Wesley,1993.<BR>M. Morris Mano (UCLA), <I>Digital Design,</I> Second Edition, Prentice-Hall, 1991.<BR>Franklin P. Prosser and David E. Winkel, <I>The Art of Digital Design:An Introduction to Top-Down Design, </I>Second Edition, Prentice-Hall, Inc.,1987.<BR>Mentor Graphics, various Bold_Browser documents, to be listed on a separate handout, coving QuickVHDL, Synthesis, System Design Station, and System-1076.<BR></BLOCKQUOTE><H3>Lecture Notes: </H3><BLOCKQUOTE><!WA3><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/Course_Guide_F96.ps">Course Guide</A></BLOCKQUOTE><BLOCKQUOTE><!WA4><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/Agenda_F96.ps">Course Agenda </A></BLOCKQUOTE><BLOCKQUOTE><!WA5><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/4-Pole_Stepper_F96.ps">4-Pole Stepper Motor Control</A> </BLOCKQUOTE><BLOCKQUOTE><!WA6><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/MGC_Documents_CSD-I.ps">Mentor Graphics Documents</A></BLOCKQUOTE><BLOCKQUOTE><!WA7><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/Levels_of_Detail.ps">Levels of Detail in Design</A></BLOCKQUOTE><BLOCKQUOTE><!WA8><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/MemGen.ps">Xilinx memgen for ROM/RAM</A></BLOCKQUOTE><BLOCKQUOTE><!WA9><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/IEEE_up_Standard.ps">IEEE Microprocesor Assembly Language Standard</A></BLOCKQUOTE><BLOCKQUOTE><!WA10><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/MUFOM_Example.ps">IEEE Standard Format for Microprocessor Object Modules</A></BLOCKQUOTE><H3>Homework Assignments: </H3><BLOCKQUOTE><!WA11><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/TeamAsgnF96.ps">Team Assignment</A><BLOCKQUOTE><!WA12><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/HW_Cover_Sheet.ps">Homework coverpage</A></BLOCKQUOTE><BLOCKQUOTE><!WA13><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/HW1.ps">HW1: Stepper-Motor Controller</A></BLOCKQUOTE><BLOCKQUOTE><!WA14><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/HW2.ps">HW2: Xilinx FPGA Tutorial</A></BLOCKQUOTE><BLOCKQUOTE><!WA15><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/HW3_VHDL.ps">HW3: QuickHDL & VHDLWrite Tutorial</A></BLOCKQUOTE><BLOCKQUOTE><!WA16><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/HW4_Autologic_II.ps">HW4: Autologic II Tutorial</A></BLOCKQUOTE><BLOCKQUOTE><!WA17><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/HW5_Roulette.ps">HW5: Roulette Wheel Design</A></BLOCKQUOTE><BLOCKQUOTE><!WA18><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/HW6_Proposal.ps">HW6: Term Project Proposal</A></BLOCKQUOTE></BLOCKQUOTE><BLOCKQUOTE><!WA19><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/Oral_Specs_F96.ps">Guidlines for Oral Presentations</A></BLOCKQUOTE><H3>Previous Examinations:</H3><BLOCKQUOTE><!WA20><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/Exam_F95.ps">Fall 95 Midterm Examination</A></BLOCKQUOTE><H3>Lab/Design Projects: </H3><BLOCKQUOTE><!WA21><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/SPDT_Debounce.ps">Switch Debouncing Circuits</A></BLOCKQUOTE><BLOCKQUOTE><!WA22><A HREF="http://wizard.cse.nd.edu/class_data/cse422/www/SPST_Debounce.ps">Switch Debounce, Sync, and Single-Pulse Circuit</A></BLOCKQUOTE><H3>Web Sites of Related Courses:</H3><BLOCKQUOTE><!WA23><A HREF="http://www.xilinx.com/">Xilinx Homepage<BR><!WA24><A HREF="http://www.erc.msstate.edu/~reese/vhdl_synthesis/icas_comb.html#index">Notes on Logic Synthesis with VHDL Combinational Logic</A> <BR></BODY></HTML>⌨️ 快捷键说明
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