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<HTML><HEAD><TITLE>CIS 629: Computer Architecture, Fall 1996</TITLE></HEAD><BODY> <HR><div align=center><H1>CIS 629: Computer Architecture</H1><H2>Fall 1996</H2><H2>Instructor: <!WA0><A HREF="http://www.cs.uoregon.edu/~malony/"> Allen D. Malony</A></H2><H2><kbd>URL: http://www.cs.uoregon.edu/classes/cis629/</kbd></H2></div><HR>Computer architecture is the science and art of selecting andinterconnecting hardware components to create a computer that meetsfunctional, performance and cost goals.This course qualitatively and quantitatively examines computer designtradeoffs.Our focus will be on processor architectures, memory systems, andmultiprocessor machines.In particular, we will study:instruction-level parallelism (super-pipelining and super-scalaraRISC processor design);memory hierarchies, cache systems, and coherency mechanisms; andmultiprocessor architectures and parallel computing.<UL> <LI> <!WA1><A HREF="#new">Announcements</A> <LI> <!WA2><A HREF="#instructor">Instructor</A> <LI> <!WA3><A HREF="#lecture">Lecture</A> <LI> <!WA4><A HREF="#text">Required Text</A> <LI> <!WA5><A HREF="#reference">Reference Text</A> <LI> <!WA6><A HREF="#readings">Readings</A> <LI> <!WA7><A HREF="#notes">Lecture Notes</A> <LI> <!WA8><A HREF="#hw">Homeworks</A> <LI> <!WA9><A HREF="#exams">Examinations</A> <LI> <!WA10><A HREF="#programming">Programming</A> <LI> <!WA11><A HREF="#project">Project</A> <LI> <!WA12><A HREF="#grading">Grading</A> <LI> <!WA13><A HREF="#schedule">Approximate Schedule</A> <LI> <!WA14><A HREF="#tutorials">Tutorials</A> <LI> <!WA15><A HREF="#tools">Tools</A> <LI> <!WA16><A HREF="#miscellanea">Miscellanea</A> <LI> <!WA17><A HREF="#misconduct">Academic Misconduct</A> <LI> <!WA18><A HREF="#class">Class Roster</A></UL><HR><H3><A NAME="new">Announcements</A></H3><font color="purple"><UL> <LI> 10/1: Required text is available in the bookstore. <LI> 10/1: Readings packet 1 is available in the bookstore. <LI> 10/2: Please read papers 1-4 in readings packet 1. <LI> 10/7: Please read paper 5 in readings packet 1. <LI> 10/22: Please read papers 6, 7, and 8 in readings packet 1. <LI> 11/15: Please read cache coherence papers in readings packet 2. <LI> 11/15: Please read STiNG paper in readings packet 2. <LI> 11/15: Please do assignment describe in the Programming section.</UL></font><H3><A NAME="instructor">Instructor</A><!WA19><A HREF="http://www.cs.uoregon.edu/~malony/">Allen D. Malony</A></H3><pre> Office: 307 Deschutes Hall Email: malony@cs.uoregon.edu Office hours: Monday/Wednesday, 11:00-12:00 or by appointment</pre><H3><A NAME="lecture">Lecture</A></H3><pre> Time: Tuesday/Thursday, 14:00 - 15:20 Place: 135 Gilbert Hall</pre><H3><A NAME="text">Required Text</A></H3><pre> Harold S. Stone, High-Performance Computer Architecture, Third Edition, Addison-Wesley, 1993.</pre><H3><A NAME="reference">Reference Text</A></H3><pre> John L. Hennessy and David A. Patterson, <!WA20><A HREF="http://Literary.COM//mkp/new/hp2e/hp2e_index.shtml">Computer Architecture: A Quantitative Approach</A>, Morgan Kaufmann Publishers, Second Edition, 1996.</pre><H3><A NAME="readings">Readings</A></H3><UL> <LI> 1. <!WA21><A HREF="http://www.cs.uoregon.edu/classes/cis629/readings1.ps">Selected Readings -- Background and Processor Design</A> <LI> 2. Selected Readings -- Memory System Architectures <LI> 3. Selected Readings -- Multiprocessor Architectures</UL>Each part of the course will be accompanied by a set of papers from thecomputer architecture literature.The reading packets will be available in the bookstore.<H3><A NAME="notes">Lecture Notes</A></H3>Lecture notes will be made available as they are developed.See links in schedule.<H3><A NAME="hw">Homework</A></H3>There will be two homework assignments.Many problems will require the review of material that is touched upon,but not covered in depth in class.Assignments will be due in class on the due date.NO LATE ASSIGNMENTS WILL BE ACCEPTED, except under extreme non-academiccircumstances discussed with the instructor at least one week before theassignment is due.<UL> <LI> <!WA22><A HREF="http://www.cs.uoregon.edu/classes/cis629/Homework/homework-1.ps">Homework 1</A>; <!WA23><A HREF="http://www.cs.uoregon.edu/classes/cis629/HP-book/Figures/3.10.ps">Figure 3.10</A> and <!WA24><A HREF="http://www.cs.uoregon.edu/classes/cis629/HP-book/Figures/3.44.ps">Figure 3.44</A>; <!WA25><A HREF="http://www.cs.uoregon.edu/classes/cis629/Homework/homework-1.errata">Errata</A>; <!WA26><A HREF="http://www.cs.uoregon.edu/classes/cis629/Homework/solutions-1.ps">Solutions</A>. <LI> Homework 2: This has been combined with the programming assignment.</UL><H3><A NAME="exams">Examinations</A></H3><pre> <!WA27><A HREF="http://www.cs.uoregon.edu/classes/cis629/Midterm/midterm.ps">Midterm</A>: Takehome, Oct. 31 (Halloween); Due: Nov. 5</pre>Please advise me of any conflicts with these likely exam times beforethe end of the second week of classes.<H3><A NAME="programming">Programming</A></H3>The topic of the programming assignment is cache simulation.The programming assigment is combined with the second homework assignment.There are two parts.<P>Part 1.Run the following trace files through the Dinero cachesimulator. Use the Dinero server found in this WEB page.<UL> <LI> cc1 - found in Dinero server options <LI> spice - found in Dinero server options <LI> tex - found in Dinero server options</UL>Show results for different levels of cache size (unified and split),associativity, and block sizes. Explain the results that you see.<P>Part 2.The following sample code models an 8 Kbyte, direct-mapped cache with32-byte lines (blocks) (2^5). It treats reads and writes in the samewas,as a simple "reference". Included is only the routine that checks for areference in the cache and accummulates total references and misses. Notincluded are the I/O routines to read in a reference trace (assuming itcomes from a file or stdio) and to produce output statistics.<pre>#include <stdio.h>#include <assert.h>#define CACHE_SIZE 8192#define BLOCK_SHIFT 5long tags[CACHE_SIZE >> BLOCK_SHIFT];long references=0, misses=0;void Reference(long address){ int index = (address & (CACHE_SIZE-1)) >> BLOCK_SHIFT; long tag = address >> BLOCK_SHIFT; if (tags[index] != tag) { misses++; tags[index] = tag; } references++;}</pre>a. Add necessary I/O support (as briefly described) to the code above to make this into a cache simulation program that takes a reference trace file.<P>b. Write a routine to model a 2-way and a 4-way set associative cache of the same size.<P>c. Demonstrate the operation of all three simulators with three programs of your own choosing. That is, find or write three programs (they can be simple) from which you can capture address references to drive your simulators. (One thought is to get three Linpack codes.) Note, you need to modify the programs to capture references; concentrate only on data references.<P>This assignment will be due on Dec. 3.<H3><A NAME="project">Term Project</A></H3>The term project will be to write a paper that surveys an area withincomputer architecture.The paper should: <UL> <LI> summarize work in an area, giving extensive references (6 at least) <LI> present opinions of others for or against various options (again, with references) <LI> conclude with your opinion of the strengths and weaknesses of the arguments given </UL>You will be graded on the completeness of your survey, the accuracy of yoursummaries, and the support you give for your opinions.Some possible survey topics are: <UL> <LI> compiler transformations to improve memory behavior, <LI> superscalar & superpipelined processors vs. VLIW <LI> effect on architecture of changing technology (you might consider different types of technology) <LI> high-performance I/O (e.g., for storage or network communication) <LI> contrast of state-of-the-art processors <LI> massively parallel processing systems <LI> scalable architecture technologies <LI> some aspect of the history of computer architecture </UL>The topic chosen should be something that you are particularly interestedin.There are many references for papers including: <UL> <LI> Proc. of the Int'l. Symposium on Computer Architecture (ISCA) <LI> Proc. of the Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS) <LI> Int'l. Conf. on Parallel Processing (ICPP) <LI> Supercomputing Conf. <LI> Int'l. Conf. on Supercomputing (ICS) <LI> IEEE Trans. on Computers <LI> ACM Trans. on Computer Systems <LI> IEEE Computer⌨️ 快捷键说明
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