ds18b20.v

来自「基于VHDL写的DS18B20的驱动」· Verilog 代码 · 共 143 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ds18b20 is
	port(start: in std_logic;
		 io: inout std_logic;
		 clk:in std_logic;
		 thout: out std_logic_vector(3 downto 0);
		 tlout: out std_logic_vector(3 downto 0)
		);
end ds18b20;
architecture behave of ds18b20 is
	signal iodata:std_logic;
	signal dt:integer range 0 to 1000;
	signal isstart:std_logic;
	signal s:std_logic_vector(2 downto 0);
	signal s2:integer range 0 to 3;
	signal writebyte:std_logic_vector(7 downto 0);
	signal bitNum:integer;
	signal th:std_logic_vector(7 downto 0);
	signal tl:std_logic_vector(7 downto 0);
begin
	process(s,start,clk) 
	begin
		if (start='1') then
			s<="000";
			s2<=0;
			dt<=0;
			bitnum<=0;
		elsif (clk'event and clk='1') then
			case s is
			when "000"=>               --复位
				if (dt<10) then
					iodata<='1';
					dt<=dt+1;
				else if (dt<500) then
					iodata<='0';
					dt<=dt+1;
					else if (dt<1000) then
						iodata<='Z';
						dt<=dt+1;
						else dt<=0;
							s<="001";
							end if;
					end if;
				end if;
				
			when "001"=>		
				if s2=0 then writebyte<="11001100"; end if;	--写入0XCC,SKIP ROM
				if s2=1 then writebyte<="01000100"; end if;	--写入0X44,CONVERT
				if s2=2 then writebyte<="11001100"; end if;	--写入0XCC,SKIP ROM
				if s2=3 then writebyte<="10111110"; end if;	--写入0XBE,READ RAM
				if bitnum<8 then
					if (dt<5) then
						iodata<='0';
						dt<=dt+1;
					else if (dt<60) then
						iodata<=writebyte(bitnum);
						dt<=dt+1;
						else if (dt<70) then
							iodata<='Z';
							dt<=dt+1;
							else dt<=0;
								 bitnum<=bitnum+1;
							end if;
						end if;
					end if;
				else 	bitnum<=0;
						if s2=0 then s2<=1;
						elsif s2=1 then s<="010";
						elsif s2=2 then s2<=3;
						elsif s2=3 then s<="011";
						end if;
				end if;
				
			when "010"=>							--wait for convert
				if (dt<1000) then
					dt<=dt+1;
				else dt<=0;
					 s2<=2;
					 s<="000";
				end if;
				
			when "011"=>							--read temper_L
				if bitnum<8 then
					if (dt<2) then
						iodata<='0';
						dt<=dt+1;
					else if (dt<4) then
						iodata<='Z';
						dt<=dt+1;
						else if (dt<14) then
							tl(bitnum)<=io;
							dt<=dt+1;
							else if (dt<65) then
									iodata<='Z';
									dt<=dt+1;
								else  dt<=0;
								  bitnum<=bitnum+1;
								end if;
							end if;
						end if;
					end if;
				else 	bitnum<=0;
						s<="100";
				end if;
			
			when "100"=>					--read temper_H
				if bitnum<8 then
					if (dt<2) then
						iodata<='0';
						dt<=dt+1;
					else if (dt<4) then
						iodata<='Z';
						dt<=dt+1;
						else if (dt<14) then
							th(bitnum)<=io;
							dt<=dt+1;
							else if (dt<65) then
									iodata<='Z';
									dt<=dt+1;
								else  dt<=0;
								  bitnum<=bitnum+1;
								end if;
							end if;
						end if;
					end if;
				else 	bitnum<=0;
						s2<=0;
						s<="000";
				end if;
				
			when others=>
				s<="000";				
			end case;
			
		end if;
	end process;
	io<=iodata;
	thout<=th(3 downto 0);
	tlout<=tl(7 downto 4);
end behave;