ds18b20.tan.rpt

来自「基于VHDL写的DS18B20的驱动」· RPT 代码 · 共 270 行 · 第 1/5 页

+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+------------+------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From       ; To                                                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------+------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 83.63 MHz ( period = 11.958 ns )                    ; dt[10]     ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.690 ns               ;
; N/A                                     ; 85.46 MHz ( period = 11.701 ns )                    ; dt[3]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.395 ns               ;
; N/A                                     ; 85.53 MHz ( period = 11.692 ns )                    ; dt[9]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.424 ns               ;
; N/A                                     ; 85.56 MHz ( period = 11.688 ns )                    ; dt[6]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.382 ns               ;
; N/A                                     ; 86.46 MHz ( period = 11.566 ns )                    ; dt[7]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.298 ns               ;
; N/A                                     ; 86.53 MHz ( period = 11.557 ns )                    ; dt[5]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.251 ns               ;
; N/A                                     ; 86.57 MHz ( period = 11.551 ns )                    ; bitNum[21] ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.283 ns               ;
; N/A                                     ; 87.78 MHz ( period = 11.392 ns )                    ; dt[10]     ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 11.124 ns               ;
; N/A                                     ; 87.83 MHz ( period = 11.386 ns )                    ; dt[4]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.080 ns               ;
; N/A                                     ; 88.54 MHz ( period = 11.294 ns )                    ; bitNum[17] ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.026 ns               ;
; N/A                                     ; 88.61 MHz ( period = 11.285 ns )                    ; bitNum[20] ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 11.017 ns               ;
; N/A                                     ; 88.83 MHz ( period = 11.257 ns )                    ; dt[14]     ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 10.989 ns               ;
; N/A                                     ; 89.01 MHz ( period = 11.235 ns )                    ; dt[3]      ; iodata                                                                                   ; clk        ; clk      ; None                        ; None                      ; 10.936 ns               ;
; N/A                                     ; 89.42 MHz ( period = 11.183 ns )                    ; bitNum[9]  ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2 ; clk        ; clk      ; None                        ; None                      ; 10.915 ns               ;
; N/A                                     ; 89.81 MHz ( period = 11.135 ns )                    ; dt[3]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 10.829 ns               ;
; N/A                                     ; 89.88 MHz ( period = 11.126 ns )                    ; dt[9]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 10.858 ns               ;
; N/A                                     ; 89.91 MHz ( period = 11.122 ns )                    ; dt[6]      ; altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg3 ; clk        ; clk      ; None                        ; None                      ; 10.816 ns               ;