ds18b20.map.qmsg

基于VHDL写的DS18B20的驱动

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 03 19:00:27 2007 " "Info: Processing started: Sun Jun 03 19:00:27 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ds18b20 -c ds18b20 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ds18b20 -c ds18b20" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ds18b20.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ds18b20.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ds18b20-behave " "Info: Found design unit 1: ds18b20-behave" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ds18b20 " "Info: Found entity 1: ds18b20" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "I:/cyclone/ds18b20/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ds18b20 " "Info: Elaborating entity \"ds18b20\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "iodata~0 " "Warning: Converting TRI node \"iodata~0\" that feeds logic to a wire" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 16 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "writebyte\[4\] writebyte\[1\] " "Info: Duplicate register \"writebyte\[4\]\" merged to single register \"writebyte\[1\]\"" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "writebyte\[5\] writebyte\[1\] " "Info: Duplicate register \"writebyte\[5\]\" merged to single register \"writebyte\[1\]\"" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "writebyte\[7\] writebyte\[3\] " "Info: Duplicate register \"writebyte\[7\]\" merged to single register \"writebyte\[3\]\"" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "writebyte\[0\] data_in GND " "Warning: Reduced register \"writebyte\[0\]\" with stuck data_in port to stuck value GND" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "writebyte\[2\] High " "Info: Power-up level of register \"writebyte\[2\]\" is not specified -- using power-up level of High to minimize register" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "writebyte\[2\] data_in VCC " "Warning: Reduced register \"writebyte\[2\]\" with stuck data_in port to stuck value VCC" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "writebyte\[1\] writebyte\[6\] " "Info: Duplicate register \"writebyte\[1\]\" merged to single register \"writebyte\[6\]\", power-up level changed" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "thout\[1\] VCC " "Warning: Pin \"thout\[1\]\" stuck at VCC" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "thout\[2\] GND " "Warning: Pin \"thout\[2\]\" stuck at GND" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "thout\[3\] GND " "Warning: Pin \"thout\[3\]\" stuck at GND" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } } { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } } { "ds18b20.vhd" "" { Text "I:/cyclone/ds18b20/ds18b20.vhd" 32 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "iodata~en " "Info: Register \"iodata~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "233 " "Info: Implemented 233 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "217 " "Info: Implemented 217 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Allocated 141 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 03 19:00:34 2007 " "Info: Processing ended: Sun Jun 03 19:00:34 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}