ds18b20.sta.qmsg

基于VHDL写的DS18B20的驱动

{ "Info" "0" "" "Info: qsta_default_script.tcl version: 23.0.1.4" {  } {  } 0 0 "qsta_default_script.tcl version: 23.0.1.4" 0 0}
{ "Info" "0" "" "Info: Migrating assignments from quartus_tan" {  } {  } 0 0 "Migrating assignments from quartus_tan" 0 0}
{ "Warning" "0" "" "Warning: This translation should be used as a guide. Results should be checked carefully" {  } {  } 0 0 "This translation should be used as a guide. Results should be checked carefully" 0 0}
{ "Info" "0" "" "Info: ** Translating Global Settings" {  } {  } 0 0 "** Translating Global Settings" 0 0}
{ "Critical Warning" "0" "" "Critical Warning: QSF: Expected CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS to be set to 'OFF', but it is set to 'ON'" {  } {  } 1 0 "QSF: Expected CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS to be set to 'OFF', but it is set to 'ON'" 0 0}
{ "Critical Warning" "0" "" "Critical Warning:      In SDC, all clocks are related by default" {  } {  } 1 0 "     In SDC, all clocks are related by default" 0 0}
{ "Critical Warning" "0" "" "Critical Warning: QSF: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'" {  } {  } 1 0 "QSF: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'" 0 0}
{ "Critical Warning" "0" "" "Critical Warning:      In SDC, create_generated_clock auto-generates clock latency" {  } {  } 1 0 "     In SDC, create_generated_clock auto-generates clock latency" 0 0}
{ "Critical Warning" "0" "" "Critical Warning: QSF: Expected DEFAULT_HOLD_MULTICYCLE to be set to 'ONE', but it is set to 'SAME AS MULTICYCLE'" {  } {  } 1 0 "QSF: Expected DEFAULT_HOLD_MULTICYCLE to be set to 'ONE', but it is set to 'SAME AS MULTICYCLE'" 0 0}
{ "Critical Warning" "0" "" "Critical Warning:      In SDC, the Default Hold Multicycle is zero - equivalent to one in the Classic Timing Analyzer" {  } {  } 1 0 "     In SDC, the Default Hold Multicycle is zero - equivalent to one in the Classic Timing Analyzer" 0 0}
{ "Critical Warning" "0" "" "Critical Warning: QSF: Expected ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS to be set to 'ON', but it is set to 'OFF'" {  } {  } 1 0 "QSF: Expected ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS to be set to 'ON', but it is set to 'OFF'" 0 0}
{ "Critical Warning" "0" "" "Critical Warning:      Latches are always treated as synchronous elements by the TimeQuest Timing Analyzer" {  } {  } 1 0 "     Latches are always treated as synchronous elements by the TimeQuest Timing Analyzer" 0 0}
{ "Extra Info" "0" "" "Extra Info: derive_pll_clocks -use_tan_name" {  } {  } 1 0 "derive_pll_clocks -use_tan_name" 0 0}
{ "Info" "0" "" "Info: ** Translating Clocks" {  } {  } 0 0 "** Translating Clocks" 0 0}
{ "Critical Warning" "0" "" "Critical Warning: No Clock Settings defined in QSF file" {  } {  } 1 0 "No Clock Settings defined in QSF file" 0 0}
{ "Extra Info" "0" "" "Extra Info: Found 0 clock(s) in 'ds18b20.qsf'" {  } {  } 1 0 "Found 0 clock(s) in 'ds18b20.qsf'" 0 0}
{ "Warning" "0" "" "Warning: Clock Settings Summary Panel not found" {  } {  } 0 0 "Clock Settings Summary Panel not found" 0 0}
{ "Warning" "0" "" "Warning: No clocks were found in QSF or TAN.RPT files" {  } {  } 0 0 "No clocks were found in QSF or TAN.RPT files" 0 0}
{ "Info" "0" "" "Info: ** Translating Clock Latency assignments" {  } {  } 0 0 "** Translating Clock Latency assignments" 0 0}
{ "Info" "0" "" "Info: ** Translating Clock Uncertainty assignments" {  } {  } 0 0 "** Translating Clock Uncertainty assignments" 0 0}
{ "Info" "0" "" "Info: ** Translating MultiCycle assignments" {  } {  } 0 0 "** Translating MultiCycle assignments" 0 0}
{ "Info" "0" "" "Info: ** Translating Cut assignments" {  } {  } 0 0 "** Translating Cut assignments" 0 0}
{ "Info" "0" "" "Info: ** Translating Input/Output Delay assignments" {  } {  } 0 0 "** Translating Input/Output Delay assignments" 0 0}
{ "Info" "0" "" "Info: ** Translating Tpd assignments" {  } {  } 0 0 "** Translating Tpd assignments" 0 0}
{ "Info" "0" "" "Info: ** Translating Setup/Hold Relationship assignments" {  } {  } 0 0 "** Translating Setup/Hold Relationship assignments" 0 0}
{ "Info" "0" "" "Info: ** Translating Tsu/Th/Tco/Min Tco assignments" {  } {  } 0 0 "** Translating Tsu/Th/Tco/Min Tco assignments" 0 0}
{ "Info" "0" "" "Info: ** Translating HDL based assignments" {  } {  } 0 0 "** Translating HDL based assignments" 0 0}
{ "Info" "0" "" "Info: ** Checking for unsupported assignments" {  } {  } 0 0 "** Checking for unsupported assignments" 0 0}
{ "Info" "0" "" "Info: --------------------------------------------------------" {  } {  } 0 0 "--------------------------------------------------------" 0 0}
{ "Info" "0" "" "Info: Generated ds18b20.sdc" {  } {  } 0 0 "Generated ds18b20.sdc" 0 0}
{ "Info" "0" "" "Info: --------------------------------------------------------" {  } {  } 0 0 "--------------------------------------------------------" 0 0}