ds18b20.sdc

来自「基于VHDL写的DS18B20的驱动」· SDC 代码 · 共 28 行

###########################################################################
#
# Generated by : Version 6.1 Build 201 11/27/2006 SJ Full Version
#
# Project      : ds18b20
# Revision     : ds18b20
#
# Date         : Sun Jun 03 19:14:21 中国标准时间 2007
#
###########################################################################
 
 
# WARNING: Expected CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS to be set to 'OFF', but it is set to 'ON'
#          In SDC, all clocks are related by default
# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
# WARNING: Expected DEFAULT_HOLD_MULTICYCLE to be set to 'ONE', but it is set to 'SAME AS MULTICYCLE'
#          In SDC, the Default Hold Multicycle is zero - equivalent to one in the Classic Timing Analyzer
# WARNING: Expected ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS to be set to 'ON', but it is set to 'OFF'
#          Latches are always treated as synchronous elements by the TimeQuest Timing Analyzer
#
# ------------------------------------------
#
# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
#
# ------------------------------------------