ds18b20.tan.summary

基于VHDL写的DS18B20的驱动

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.391 ns
From           : ioin
To             : altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg7
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.306 ns
From           : altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg7
To             : tlout[2]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.033 ns
From           : ioin
To             : tl[0]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 83.63 MHz ( period = 11.958 ns )
From           : dt[10]
To             : altsyncram:reduce_or_rtl_0|altsyncram_3rj:auto_generated|ram_block1a0~porta_address_reg2
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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