ds18b20.map.rpt

基于VHDL写的DS18B20的驱动

;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 94    ;
;     -- 3 input functions                    ; 57    ;
;     -- 2 input functions                    ; 61    ;
;     -- 1 input functions                    ; 4     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 172   ;
;     -- arithmetic mode                      ; 45    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 15    ;
;     -- asynchronous clear/load mode         ; 53    ;
;                                             ;       ;
; Total registers                             ; 68    ;
; Total logic cells in carry chains           ; 47    ;
; I/O pins                                    ; 16    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 68    ;
; Total fan-out                               ; 870   ;
; Average fan-out                             ; 3.73  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |ds18b20                   ; 217 (217)   ; 68           ; 0           ; 16   ; 0            ; 149 (149)    ; 1 (1)             ; 67 (67)          ; 47 (47)         ; 0 (0)      ; |ds18b20            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; iodata~en                             ; Lost fanout                            ;
; writebyte[4]                          ; Merged with writebyte[1]               ;
; writebyte[5]                          ; Merged with writebyte[1]               ;
; writebyte[7]                          ; Merged with writebyte[3]               ;
; writebyte[0]                          ; Stuck at GND due to stuck port data_in ;
; writebyte[2]                          ; Stuck at VCC due to stuck port data_in ;
; writebyte[1]                          ; Merged with writebyte[6]               ;
; Total Number of Removed Registers = 7 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 68    ;
; Number of registers using Synchronous Clear  ; 15    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 51    ;
; Number of registers using Asynchronous Load  ; 2     ;
; Number of registers using Clock Enable       ; 50    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; bitNum[31]                             ; 37      ;
; s[1]                                   ; 23      ;
; s[0]                                   ; 26      ;
; s[2]                                   ; 22      ;
; bitNum[0]                              ; 13      ;
; Total number of inverted registers = 5 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |ds18b20|writebyte[6]      ;
; 14:1               ; 2 bits    ; 18 LEs        ; 4 LEs                ; 14 LEs                 ; Yes        ; |ds18b20|s2[1]             ;
; 14:1               ; 32 bits   ; 288 LEs       ; 32 LEs               ; 256 LEs                ; Yes        ; |ds18b20|bitNum[0]         ;
; 16:1               ; 15 bits   ; 150 LEs       ; 15 LEs               ; 135 LEs                ; Yes        ; |ds18b20|dt[0]             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sun Jun 03 19:00:27 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ds18b20 -c ds18b20
Info: Found 2 design units, including 1 entities, in source file ds18b20.vhd
    Info: Found design unit 1: ds18b20-behave
    Info: Found entity 1: ds18b20
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "ds18b20" for the top level hierarchy
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "iodata~0" that feeds logic to a wire
Info: Duplicate registers merged to single register
    Info: Duplicate register "writebyte[4]" merged to single register "writebyte[1]"
    Info: Duplicate register "writebyte[5]" merged to single register "writebyte[1]"
    Info: Duplicate register "writebyte[7]" merged to single register "writebyte[3]"
Warning: Reduced register "writebyte[0]" with stuck data_in port to stuck value GND
Info: Power-up level of register "writebyte[2]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "writebyte[2]" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "writebyte[1]" merged to single register "writebyte[6]", power-up level changed
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "thout[1]" stuck at VCC
    Warning: Pin "thout[2]" stuck at GND
    Warning: Pin "thout[3]" stuck at GND
Info: Registers with preset signals will power-up high
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "iodata~en" lost all its fanouts during netlist optimizations.
Info: Implemented 233 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 13 output pins
    Info: Implemented 217 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Allocated 141 megabytes of memory during processing
    Info: Processing ended: Sun Jun 03 19:00:34 2007
    Info: Elapsed time: 00:00:07