📄 ethernet.c
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{
if (pattern == 0x00)
pattern = 0x80;
BufferPool[FIRST_TX_BUF+5][index] = pattern;
}
/*--------------------------------------------*/
/* Buffer[6]: Load "Increment from 0" pattern */
/*--------------------------------------------*/
for (index = 12; index < (BUFFER_SIZE-4); index++)
{
BufferPool[FIRST_TX_BUF+6][index] = index-2;
}
/*----------------------------------------------*/
/* Buffer[7]: Load "Decrement from 255" pattern */
/*----------------------------------------------*/
for (index = 12; index < (BUFFER_SIZE-4); index++)
{
BufferPool[FIRST_TX_BUF+7][index] = (257-index);
}
/*-----------------------------------------------*/
/* Load destination addresses, source addresses, */
/* and type/length field into each Tx buffer */
/*-----------------------------------------------*/
int bufcount = 0;
while (bufcount < 8)
{
BufferPool[FIRST_TX_BUF + bufcount][0] = 0x00;
BufferPool[FIRST_TX_BUF + bufcount][6] = 0x00;
BufferPool[FIRST_TX_BUF + bufcount][1] = 0x19;
BufferPool[FIRST_TX_BUF + bufcount][7] = 0x19;
BufferPool[FIRST_TX_BUF + bufcount][2] = 0x22;
BufferPool[FIRST_TX_BUF + bufcount][8] = 0x22;
BufferPool[FIRST_TX_BUF + bufcount][3] = 0x33;
BufferPool[FIRST_TX_BUF + bufcount][9] = 0x33;
BufferPool[FIRST_TX_BUF + bufcount][4] = 0x48;
BufferPool[FIRST_TX_BUF + bufcount][10] = 0x48;
BufferPool[FIRST_TX_BUF + bufcount][5] = 0x55;
BufferPool[FIRST_TX_BUF + bufcount][11] = 0x55;
BufferPool[FIRST_TX_BUF + bufcount][12] = 0x00;
BufferPool[FIRST_TX_BUF + bufcount][13] = 0xEE;
bufcount++;
}
} /* end of LoadTxBuffers */
/*------------------------------------------------------------------------
*
* FUNCTION NAME: SCC1Init
*
*
* DESCRIPTION:
*
* SCC1 Ethernet Initialization Routine.
*
* EXTERNAL EFFECT:
*
* Parameter RAM and various registers on the 860 including interrupt
* related registers and port registers. This function, when complete,
* will initiate or start the transfer of 8 Ethernet frames of data. For
* this simple example, each frame encompasses one BD of data.
*
* PARAMETERS: None
*
* RETURNS: None
*
*-----------------------------------------------------------------------*/
void SCC1Init()
{
/*****************************/
/* Configure Pins and Clocks */
/*****************************/
/*---------------------------------------------*/
/* Configure Port A pins to enable RXD1, TXD1. */
/*---------------------------------------------*/
IMMR->pio_papar |= 0x0003;
/*------------------------------------------------------*/
/* These two bits must be zero when these two port A */
/* pins are configured as on-chip dedicated peripheral. */
/*------------------------------------------------------*/
IMMR->pio_padir &= 0xFFFC;
/*-------------------------------------------------------------------*/
/* Initialize baud rate generator. Our Motorola ADS target is */
/* configured to have a 24Mhz clock out of the system PLL. The 24Mhz */
/* internal clock will be divided down by 12 to give a baud clock of */
/* 2Mhz. CD bits will be programmed to 0xB. They are not programmed */
/* to 0xC because total divide ratio is CD value+1 {can never divide */
/* by 0}. */
/*-------------------------------------------------------------------*/
IMMR->brgc4 = (0x00010016); /* Enable BRG with division factor 12 */
/*---------------------------------------------------------*/ /* Initialize the SI Clock Route Register (SICR) for SCC1. */
/* */
/* - Connect SCC1 to NMSI, */
/* - Transmit Clock = BRG4, Receive Clock = BRG4 */
/*---------------------------------------------------------*/ IMMR->si_sicr &= (0xFFFFFF00); /* Clear previous scc1 setting */
IMMR->si_sicr |= (0x0000001B); /* Setup scc1 */
/**************************************************/
/* Ethernet Specific Parameter RAM Initialization */
/**************************************************/
IMMR->PRAM[PAGE1].enet_scc.c_pres = ENET_C_PRES; /* CRC Preset */
IMMR->PRAM[PAGE1].enet_scc.c_mask = ENET_C_MASK; /* Constant MASK for CRC */
IMMR->PRAM[PAGE1].enet_scc.crcec = ALL_ZEROS; /* CRC Error Counter */
IMMR->PRAM[PAGE1].enet_scc.alec = ALL_ZEROS; /* Align. Error Counter */
IMMR->PRAM[PAGE1].enet_scc.disfc = ALL_ZEROS; /* Discard Frame Counter */
IMMR->PRAM[PAGE1].enet_scc.pads = ENET_PAD; /* Short Frame PAD Char. */
IMMR->PRAM[PAGE1].enet_scc.ret_lim = ENET_RET_LIM;/* Retry Limit Threshold */
IMMR->PRAM[PAGE1].enet_scc.mflr = ENET_MFLR; /* Max Frame Length Reg. */
IMMR->PRAM[PAGE1].enet_scc.minflr = ENET_MINFLR; /* Min Frame Length Reg. */
IMMR->PRAM[PAGE1].enet_scc.maxd1 = ENET_MDMA; /* Max DMA1 Length Reg. */
IMMR->PRAM[PAGE1].enet_scc.maxd2 = ENET_MDMA; /* Max DMA2 Length Reg. */
IMMR->PRAM[PAGE1].enet_scc.gaddr1 = ALL_ZEROS; /* Group Addr. Filter 1 */
IMMR->PRAM[PAGE1].enet_scc.gaddr2 = ALL_ZEROS; /* Group Addr. Filter 2 */
IMMR->PRAM[PAGE1].enet_scc.gaddr3 = ALL_ZEROS; /* Group Addr. Filter 3 */
IMMR->PRAM[PAGE1].enet_scc.gaddr4 = ALL_ZEROS; /* Group Addr. Filter 4 */
IMMR->PRAM[PAGE1].enet_scc.paddr_h = ENET_PADDR_H;/* Phys. Addr. 1 (MSB) */
IMMR->PRAM[PAGE1].enet_scc.paddr_m = ENET_PADDR; /* Phys. Addr. 1 */
IMMR->PRAM[PAGE1].enet_scc.paddr_l = ENET_PADDR_L /* Phys. Addr. 1 (LSB) */
IMMR->PRAM[PAGE1].enet_scc.p_per = ALL_ZEROS; /* Persistence */
IMMR->PRAM[PAGE1].enet_scc.iaddr1 = ALL_ZEROS; /* Ind. Addr. Filter 1 */
IMMR->PRAM[PAGE1].enet_scc.iaddr2 = ALL_ZEROS; /* Ind. Addr. Filter 2 */
IMMR->PRAM[PAGE1].enet_scc.iaddr3 = ALL_ZEROS; /* Ind. Addr. Filter 3 */
IMMR->PRAM[PAGE1].enet_scc.iaddr4 = ALL_ZEROS; /* Ind. Addr. Filter 4 */
IMMR->PRAM[PAGE1].enet_scc.taddr_h = ALL_ZEROS; /* Temp Address (MSB) */
IMMR->PRAM[PAGE1].enet_scc.taddr_m = ALL_ZEROS; /* Temp Address */
IMMR->PRAM[PAGE1].enet_scc.taddr_l = ALL_ZEROS; /* Temp Address (LSB) */
/********************************************************/
/* Common To All Protocols Parameter RAM Initialization */
/********************************************************/
/*---------------------------------*/
/* Set RXBD tbl start at Dual Port */
/*---------------------------------*/
IMMR->PRAM[PAGE1].enet_scc.rbase = (UHWORD)&RxTxBD->RxBD[0];
/*---------------------------------*/
/* Set TXBD tbl start at Dual Port */
/*---------------------------------*/
IMMR->PRAM[PAGE1].enet_scc.tbase = (UHWORD)&RxTxBD->TxBD[0];
/*--------------------------------------*/
/* Set RFCR,TFCR -- Rx,Tx Function Code */
/*--------------------------------------*/
IMMR->PRAM[PAGE1].enet_scc.rfcr = 0x18; /* Normal Operation and
Motorola byte ordering */
IMMR->PRAM[PAGE1].enet_scc.tfcr = 0x18; /* Motorola byte ordering,
Normal access */
/*-----------------------------------------*/
/* Set MRBLR -- Max. Receive Buffer Length */
/* (Must be a multiple of 4, so use 1520) */
/*-----------------------------------------*/
IMMR->PRAM[PAGE1].enet_scc.mrblr = ENET_MDMA;
/****************************/
/* Register Initializations */
/****************************/
/*-----------------------------------------------------*/
/* Initialize GSMR_H for normal operation */
/*-----------------------------------------------------*/
IMMR->scc_regs[SCC1_REG].scc_gsmr_h = 0;
/*--------------------------------------------------------*/
/* Initialize GSMR_L: */
/* */
/* TCI = 1, TSNC = 10, TPL = 100, DIAG = 01, MODE = 1100 */
/*--------------------------------------------------------*/
IMMR->scc_regs[SCC1_REG].scc_gsmr_l = 0x1088004C;
/*-------------------*/
/* Set DSR to 0xD555 */
/*-------------------*/
IMMR->scc_regs[SCC1_REG].scc_dsr = ENET_DSR;
/*------------------------------------------------*/
/* Initialize PSMR: */
/* */
/* IAM = 0, CRC = 10 (32-bit), LPB = 1, NIB = 101 */
/*------------------------------------------------*/
IMMR->scc_regs[SCC1_REG].scc_psmr = 0x084A;
/*-----------------------------------------*/
/* Clear SCCE Register by writing all 1's. */
/*-----------------------------------------*/
IMMR->scc_regs[SCC1_REG].scc_scce = ALL_ONES;
/**************/
/* Interrupts */
/**************/
/*---------------------------------------------*/
/* Enable SCC1 Interrupts to the CP Interrupt */
/* Controller by writing 0x40000000 to CIMR */
/*---------------------------------------------*/
IMMR->cpmi_cimr = CIMR_SCC1;
/*-------------------------------------------------------------*/
/* Clear Pending Interrupts in CIPR -- Clear bits by writing 1 */
/*-------------------------------------------------------------*/
IMMR->cpmi_cipr = ALL_ONES;
/*-----------------------------------------------*/
/* Set Appropriate Interrupt Level Bit in SIMASK */
/*-----------------------------------------------*/
switch(INTERRUPT_LEVEL)
{
case 0:
IMMR->siu_simask = SIMASK_LVM0;
break;
case 1:
IMMR->siu_simask = SIMASK_LVM1;
break;
case 2:
IMMR->siu_simask = SIMASK_LVM2;
break;
case 3:
IMMR->siu_simask = SIMASK_LVM3;
break;
case 4:
IMMR->siu_simask = SIMASK_LVM4;
break;
case 5:
IMMR->siu_simask = SIMASK_LVM5;
break;
case 6:
IMMR->siu_simask = SIMASK_LVM6;
break;
case 7:
IMMR->siu_simask = SIMASK_LVM7;
break;
default:
break; /* Bad value */
} /* end switch */
/*------------------------------------------*/
/* Set SCCM for interrupts on TXE, RXF, TXB */
/*------------------------------------------*/
IMMR->scc_regs[SCC1_REG].scc_sccm = 0x001A;
/*----------------------------------------------------------------*/
/* Write CICR to Configure SCC1 Interrupt Priority Settings: */
/* */
/* SCC Priorities */
/* SCC1 - Highest Priority */
/* IRL0-IRL2 (Interrupt Request Level) = Constant set by user */
/* HP0-HP4 (Highest Priority) = Original Priority */
/* IEN = Enable CPM Interrupts */
/*----------------------------------------------------------------*/
IMMR->cpmi_cicr = 0x000E11F80 | (INTERRUPT_LEVEL << 13);
/*-----------------------------------------*/ /* Enable External Interrupts at CPU level */
/*-----------------------------------------*/
#ifdef MetaWare
_ASM(" mtspr 80, 0 "); /* Enable EE Bit in MSR */
#else
#ifdef Diab
asm(" mtspr 80, 0 "); /* Enable EE Bit in MSR */
#endif
#endif
/*-----------------------------------------------------------------*/
/* Issue Init RX & TX Parameters Command for SCC1. This command to */
/* the CP lets it know to reinitialize SCC1 with the new parameter */
/* RAM values. When the ENT/ENR bits are set below Hunt Mode will */
/* begin automatically. */
/*-----------------------------------------------------------------*/
while ((IMMR->cp_cr & CPCR_FLG) != READY_TO_RX_CMD);
IMMR->cp_cr = CPCR_INIT_TX_RX_PARAMS |
CPCR_SCC1_CH |
CPCR_FLG; /* ISSUE COMMAND */
while ((IMMR->cp_cr & CPCR_FLG) != READY_TO_RX_CMD);
/*-------------------------------------------------------------*/
/* Set the ENT/ENR bits in the GSMR -- Enable Transmit/Receive */
/*-------------------------------------------------------------*/
IMMR->scc_regs[SCC1_REG].scc_gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR;
} /* end SCC1Init() */
/*--------------------------------------------------------------------------
*
* FUNCTION NAME: InterruptInit
*
*
* DESCRIPTION:
*
* Copy Interrupt Handler code from its current address to the
* specified PowerPC Interrupt Vector.
*
* EXTERNAL EFFECTS:
*
* PARAMETERS:
*
* interrupt_vector -- address to which interrupt code should be copied
* interrupt_code -- current address of interrupt code
*
* RETURNS: NONE
*
*--------------------------------------------------------------------------*/
void InterruptInit(UWORD *interrupt_vector,
UWORD interrupt_code[])
{
UHWORD index;
UWORD *instruction;
UWORD *next_vector;
next_vector = (interrupt_vector + VECTOR_BLOCK_LEN); /* next vector entry */
for(instruction = interrupt_vector, index = 0; instruction < next_vector;
instruction++, index++)
*instruction = interrupt_code[index];
} /* end InterruptInit */
/*--------------------------------------------------------------------------
*
* FUNCTION NAME: BDRxError
*
* DESCRIPTION:
*
* Return TRUE if Buffer Descriptor Status bd_cstatus indicates Receive
* Error; Return FALSE otherwise note Receive Errors are as follows:
** 0x80: DPLL Error (DE)
* 0x20: Length Violation (LG)
* 0x10: Non-Octet Aligned (NO)
* 0x8: Rx Abort Sequence (AB)
* 0x4: Rx CRC Error (CR)
* 0x2: Overrun (OV)
* 0x1: Carrier Detect Lost (CD)
** EXTERNAL EFFECTS: None
*
* PARAMETERS:
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