isa 10m网卡电路设计.drc

来自「ISA 10M网卡电路设计,对电路开发很有帮助」· DRC 代码 · 共 24 行

Protel Design System Design Rule Check
PCB File : \Protel DXP 2004\Design\chapter16\ISA 10M网卡电路设计.PCBDOC
Date     : 2005-7-19
Time     : 11:14:06

Processing Rule : Clearance Constraint (Gap=0.25mm) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Width Constraint (Min=0.2mm) (Max=0.3mm) (Preferred=0.2mm) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=0.3mm) (Max=0.5mm) (Preferred=0.5mm) (InNet('VCC') Or InNet('VEE') Or InNet('+12V') Or InNet('GND'))
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:14