📄 vectors.s
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ldr r0,=BDIDES0
ldr r1,=0x40000000 ;BDIDESn 复位值应为 0x40000000
str r1,[r0]
ldr r0,=BDIDES1
ldr r1,=0x40000000 ;BDIDESn 复位值应为 0x40000000
str r1,[r0]
;设置存储器控制寄存器，存储器的配置数据都存储在SMRDATA为起始地址的数据表中，
;下面的代码可以一次将预先配置好的初始化数据存入与存储器控制器相关的13个寄存
;器，这些寄存器则是以0x01c80000为起始地址的13个连续的32位寄存器
ldr r0,=SMRDATA
ldmia r0,{r1-r13}
ldr r0,=0x01c80000 ; BWSCON存储控制寄存器地址
stmia r0,{r1-r13}
BL relocate
BL initStack
BL start_kernel
undefined_instruction
B undefined_instruction
;**************************************************************************************************
; Software Interrupt Handler
;**************************************************************************************************
software_interrupt
ldr sp, =StackSvc ; Initialize SP in SVC mode
STMFD SP!, {R0-R7} ; PUSH WORKING REGISTERS ONTO IRQ STACK
MOV R0, SP ; Save IRQ stack pointer
MOV R1, LR ; Save PC for return address to task
MRS R2, SPSR ; Copy SPSR (i.e. interrupted task's CPSR) to R2
MSR CPSR_c, #(NO_INT | SYS32_MODE)
; SAVE TASK'S CONTEXT ONTO TASK'S STACK
STMFD SP!, {R1} ; Push task's Return PC
STMFD SP!, {LR} ; Push task's LR
STMFD SP!, {R8-R12} ; Push task's R12-R8
MOV R12, R0
LDMFD R12!, {R3-R10} ; Move task's R0-R7 from IRQ stack to SVC stack
STMFD SP!, {R3-R10}
STMFD SP!, {R2} ; Push task's CPSR (i.e. SVC's SPSR)
MSR CPSR_c, #(NO_INT | SVC32_MODE)
LDR R8, [R1,#-4] ; get SWI ID in ARM status
BIC R8, R8, #0xFF000000
LDMFD SP!, {R0-R7} ; Restore registers R0-R7, which are parameters from user mode
MSR CPSR_c, #SYS32_MODE ; Enter SYS32 mode and enable interrupt
ldr lr,=swi_exit
ldr R9,=syscall_table
ldr pc,[R9,R8,LSL#2]
swi_exit
mov r1,sp
str r0,[r1,#+4] ;Save the return value to stack to replace the previous
;value of r0 with the return value.
b comm_exit
;**************************************************************************************************
; Prefetch Abort Exception handler
;**************************************************************************************************
prefetch_abort
B prefetch_abort
;**************************************************************************************************
; Data Abort Exception handler
;**************************************************************************************************
data_abort
B data_abort
;**************************************************************************************************
; Prefetch Abort Exception handler
;**************************************************************************************************
not_used
B not_used
;**************************************************************************************************
; IRQ handler ( Vectored Interrupt Enabled )
;**************************************************************************************************
irq
B irq
;**************************************************************************************************
; FIQ handler
;**************************************************************************************************
fiq
B fiq
;**************************************************************************************************
; Timer 0 handler
;**************************************************************************************************
handle_TIMER0
SAVE_IRQ_CONTEXT
MSR CPSR_c, #(NO_INT |SYS32_MODE) ; Disable interrupt
ldr lr,=comm_exit ; Set the return address
ldr pc, =tm_isr ; Call the ISR
;**************************************************************************************************
; Default ISR Handler
;**************************************************************************************************
handle_default
SAVE_IRQ_CONTEXT
MSR CPSR_c, #(NO_INT |SYS32_MODE) ; Disable interrupt
ldr lr,=comm_exit ; Set the return address
ldr pc, =default_isr ; Call Default ISR
;**************************************************************************************************
; Commonly Used Code to Exit Interrupt
;**************************************************************************************************
comm_exit
RESTORE_IRQ_CONTEXT
;**************************************************************************************************
; Relocate code from ROM to RAM, including RO, RW,etc
;**************************************************************************************************
relocate
mov r7, lr
ldr r0, KERNEL_RW_DATA_rom_start
ldr r1, KERNEL_RW_DATA_ram_start
ldr r2, KERNEL_RW_DATA_ram_end
bl copy_mem
mov pc,r7
;**************************************************************************************************
;* Description: copy memory
;* Parameters: R0 source memory start address
; R1 destination memory start address
; R2 destination memory end address
;**************************************************************************************************
copy_mem
ldmia r0!, {r3-r6}
stmia r1!, {r3-r6}
cmp r1, r2
ble copy_mem
mov pc,lr
;**************************************************************************************************
; initialize stack in different mode
;**************************************************************************************************
initStack
MOV R0, LR
;set SVC mode stack
MSR CPSR_c, #0xd3
LDR SP, =StackSvc
;set IRQ mode stack
MSR CPSR_c, #0xd2
LDR SP, =StackIrq
;set FIRQ mode stack
MSR CPSR_c, #0xd1
LDR SP, =StackFiq
;set Abort mode stack
MSR CPSR_c, #0xd7
LDR SP, =StackAbt
;set Undefined mode stack
MSR CPSR_c, #0xdb
LDR SP, =StackUnd
;set SYS mode stack
MSR CPSR_c, #0x5f
LDR SP, =StackUsr
MOV PC, R0
;****************************************************
;* The function for entering power down mode *
;****************************************************
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r0=CLKCON
ldr r0,=REFRESH
ldr r3,[r0]
mov r1, r3
orr r1, r1, #0x400000 ;self-refresh enable
str r1, [r0]
nop ;Wait until self-refresh is issued. May not be needed.
nop ;If the other bus master holds the bus, ...
nop ; mov r0, r0
nop
nop
nop
nop
;enter POWERDN mode
ldr r0,=CLKCON
str r2,[r0]
;wait until enter SL_IDLE,STOP mode and until wake-up
mov r0,#0xff
0 subs r0,r0,#1
bne %B0
;exit from DRAM/SDRAM self refresh mode.
ldr r0,=REFRESH
str r3,[r0]
mov pc,lr
;**************************************************************************************************
; address used in relocation
;**************************************************************************************************
IMPORT |Load$$KERNEL_CODE$$Base|
IMPORT |Image$$KERNEL_CODE$$Base|
IMPORT |Image$$KERNEL_CODE$$Limit|
IMPORT |Load$$KERNEL_RW_DATA$$Base|
IMPORT |Image$$KERNEL_RW_DATA$$Base|
IMPORT |Image$$KERNEL_RW_DATA$$Limit|
IMPORT |Image$$KERNEL_UNIT_DATA$$ZI$$Limit|
EXPORT free_ram_start_addr
; Kernel code start address in Flash
KERNEL_CODE_rom_start DCD |Load$$KERNEL_CODE$$Base|
; Kernel code start address in RAM
KERNEL_CODE_ram_start DCD |Image$$KERNEL_CODE$$Base|
; Kernel code end address in RAM
KERNEL_CODE_ram_end DCD |Image$$KERNEL_CODE$$Limit|
; Kernel data start address in Flash
KERNEL_RW_DATA_rom_start DCD |Load$$KERNEL_RW_DATA$$Base|
; Kernel data start address in RAM
KERNEL_RW_DATA_ram_start DCD |Image$$KERNEL_RW_DATA$$Base|
; Kernel data end address in RAM
KERNEL_RW_DATA_ram_end DCD |Image$$KERNEL_RW_DATA$$Limit|
free_ram_start_addr DCD |Image$$KERNEL_UNIT_DATA$$ZI$$Limit|
LTORG
SMRDATA DATA
;**************************************************************************************************
; Memory configuration has to be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy:
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz.
;**************************************************************************************************
;bank0 16bit BOOT ROM SST39VF160/SST39VF320
;bank1 8bit Nand Flash K9F2808U0A/K9F5608U0A
;bank2 16bit USB1.1 PDIUSBD12
;bank3 RTL8019
;bank4 No Uesed
;bank5 No Uesed
;bank6 16bit SDRAM
;bank7 16bit SDRAM
IF BUSWIDTH = 16
;DCD 0x11111111 ;Bank0=OM[1:0], Bank0~Bank7=16bit
DCD 0x11111001 ;Bank0=OM[1:0] 16bit BootRomSST39VF160/SST39VF320) :0x0
; |||||||- Bank1=8bit Nand Flash
; |||||--- Bank2=8bit PDIUSBD12
; ||||---- Bank3=16bit RTL8019
; |||----- Bank4~5=16bit No Uesd
; -------- Bank6~7=16bit SDRAM
ELSE ;BUSWIDTH = 32
DCD 0x22222220 ;Bank0=OM[1:0], Bank1~Bank7=32bit
ENDIF
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
IF BDRAMTYPE = "DRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN)) ;GCS6 check the MT value in parameter.a
DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN)) ;GCS7
ELSE ;"SDRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
ENDIF
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
DCD 0x10 ;SCLK power down mode, BANKSIZE 32M/32M
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
ALIGN
END
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