vectors.s

一个小型的嵌入式操作系统内核,可用于多种硬件平台

;**************************************************************************************************
;                                      EDL RTOS Kernel
;                              (c) Copyright 2005, Wu Jun
;                                   All Rights Reserved    
;                For further information, please visit http://www.enjoydigitallife.com
;
; Description:      None
; History:          
;    Date                         Remarks
;    2005-01-06                   Created initial version
;    2005-12-12                   Finished the version 2.01
;**************************************************************************************************

    INCLUDE memcfg.inc

;****************************************************************************
;中断控制预定义
INTPND	    EQU	0x01e00004
INTMOD	    EQU	0x01e00008
INTMSK	    EQU	0x01e0000c
I_ISPR	    EQU	0x01e00020
I_CMST	    EQU	0x01e0001c

;****************************************************************************
;看门狗定时器预定义
WTCON	    EQU	0x01d30000

;****************************************************************************
;系统时钟预定义
PLLCON	    EQU	0x01d80000
CLKCON	    EQU	0x01d80004
LOCKTIME    EQU	0x01d8000c
	
;****************************************************************************
;存储器控制预定义
REFRESH	    EQU 0x01c80024

;****************************************************************************
;BDMA目的寄存器
BDIDES0     EQU 0x1f80008
BDIDES1     EQU 0x1f80028

;****************************************************************************
;预定义常数（常量）
USERMODE    EQU	0x10
FIQMODE	    EQU	0x11
IRQMODE	    EQU	0x12
SVCMODE	    EQU	0x13
ABORTMODE   EQU	0x17
UNDEFMODE   EQU	0x1b
MODEMASK    EQU	0x1f
NOINT	    EQU	0xc0

;16位或者32位总线设置
	GBLA    BUSWIDTH
BUSWIDTH	SETA    16

;DRAM或者SDRAM"
	GBLS    BDRAMTYPE
BDRAMTYPE	SETS    "SDRAM"
;这个值在Flash存储器编程时应该为真
;这个值在SDRAM存储器编程时应该为假
	GBLL    PLLONSTART
PLLONSTART	SETL    {TRUE}

	GBLA	PLLCLK
PLLCLK		SETA	64000000

	[	PLLCLK = 64000000	
;系统主频计算公式如下：
;Fout = (8+ M_DIV)*Fout/[(2+P_DIV)*2]
M_DIV	EQU	56
P_DIV	EQU	3
S_DIV	EQU	1
	]




NO_INT          EQU         0xC0                         ; Mask used to disable interrupts (Both FIR and IRQ)
THUMB_BIT       EQU         0x20
SVC32_MODE      EQU         0x13
USR32_MODE      EQU         0x10
SYS32_MODE      EQU         0x1f
FIQ32_MODE      EQU         0x11
IRQ32_MODE      EQU         0x12

;**************************************************************************************************
; Import/Export Symbols
;**************************************************************************************************

    ; from  cpu\stack.S
    IMPORT  StackSvc
    IMPORT  StackIrq
    IMPORT  StackFiq
    IMPORT  StackAbt
    IMPORT  StackUnd
    IMPORT  StackUsr
    ; from  cpu\arm7\system.c
    IMPORT  sys_enterInterrupt
    IMPORT  sys_leaveInterrupt
    
    ; from  board\easyarm2200\led.c for debuging
    IMPORT  start_kernel
   
    IMPORT  syscall_table  
    IMPORT  default_isr
    IMPORT  tm_isr


    EXPORT  comm_exit
    ; referenced by mem_init() in memory management component
    EXPORT  ISR_addr_table

    CODE32
    AREA    VECTOR_START,CODE,READONLY
    ENTRY

;**************************************************************************************************
; Interrupt vectors table
;**************************************************************************************************
_code_start
    LDR PC, _bt_reset
    LDR PC, _undefined_instruction
    LDR PC, _software_interrupt
    LDR PC, _prefetch_abort
    LDR PC, _data_abort
    LDR PC, _not_used
    LDR PC, _irq
    LDR PC, _fiq
    LDR PC, _handle_EINT0
    LDR PC, _handle_EINT1
    LDR PC, _handle_EINT2
    LDR PC, _handle_EINT3
    LDR PC, _handle_EINT4567
    LDR PC, _handle_RTC_TICK
    B .
    B .
    LDR PC, _handle_ZDMA0
    LDR PC, _handle_ZDMA1
    LDR PC, _handle_BDMA0
    LDR PC, _handle_BDMA1
    LDR PC, _handle_WDT
    LDR PC, _handle_UERR01
    B .
    B .
    LDR PC, _handle_TIMER0
    LDR PC, _handle_TIMER1
    LDR PC, _handle_TIMER2
    LDR PC, _handle_TIMER3
    LDR PC, _handle_TIMER4
    LDR PC, _handle_TIMER5
    B .
    B .
    LDR PC, _handle_URXD0
    LDR PC, _handle_URXD1
    LDR PC, _handle_IIC
    LDR PC, _handle_SIO
    LDR PC, _handle_UTXD0
    LDR PC, _handle_UTXD1
    B .
    B .
    LDR PC, _handle_RTC
    B .
    B .
    B .
    B .
    B .
    B .
    B .
    LDR PC, _handle_ADC
    B .
    B .
    B .
    B .
    B .
    B .
    B .
    LDR PC,=EnterPWDN		;0xe0=EnterPWDN








;**************************************************************************************************
; Interrupt Service Routine Address Table
;**************************************************************************************************
ISR_ADDR_TABLE
_bt_reset               DCD     bt_reset
_undefined_instruction  DCD     undefined_instruction
_software_interrupt     DCD     software_interrupt
_prefetch_abort         DCD     prefetch_abort
_data_abort             DCD     data_abort
_not_used               DCD     not_used
_irq                    DCD     irq
_fiq                    DCD     fiq
_handle_ADC             DCD     default_isr
_handle_RTC             DCD     default_isr
_handle_UTXD1           DCD     default_isr
_handle_UTXD0           DCD     default_isr
_handle_SIO             DCD     default_isr
_handle_IIC             DCD     default_isr
_handle_URXD1           DCD     default_isr
_handle_URXD0           DCD     default_isr
_handle_TIMER5          DCD     default_isr
_handle_TIMER4          DCD     default_isr
_handle_TIMER3          DCD     default_isr
_handle_TIMER2          DCD     default_isr
_handle_TIMER1          DCD     default_isr
_handle_TIMER0          DCD     handle_TIMER0
_handle_UERR01          DCD     default_isr
_handle_WDT             DCD     default_isr
_handle_BDMA1           DCD     default_isr
_handle_BDMA0           DCD     default_isr
_handle_ZDMA1           DCD     default_isr
_handle_ZDMA0           DCD     default_isr
_handle_RTC_TICK        DCD     default_isr
_handle_EINT4567        DCD     default_isr
_handle_EINT3           DCD     default_isr
_handle_EINT2           DCD     default_isr
_handle_EINT1           DCD     default_isr
_handle_EINT0           DCD     default_isr

ISR_addr_table          DCD     ISR_ADDR_TABLE

    AREA    CODE_START,CODE,READONLY
;**************************************************************************************************
; address used in relocation
;**************************************************************************************************
    MACRO
$Label  SAVE_IRQ_CONTEXT
        STMFD   SP!, {R0-R7}                   ; PUSH WORKING REGISTERS ONTO IRQ STACK
        MOV     R0, SP                         ; Save   IRQ stack pointer
        SUB     R1, LR, #4                     ; Adjust PC for return address to task
        MRS     R2, SPSR                       ; Copy SPSR (i.e. interrupted task's CPSR) to R2
        ADD     SP, SP,#32
        MSR     CPSR_c, #(NO_INT | SYS32_MODE) 
                                               ; SAVE TASK'S CONTEXT ONTO TASK'S STACK
        STMFD   SP!, {R1}                      ; Push task's Return PC
        STMFD   SP!, {LR}                      ; Push task's LR
        STMFD   SP!, {R8-R12}                  ; Push task's R12-R8
        MOV     R12,   R0
        LDMFD   R12!, {R3-R10}                      ; Move task's R0-R7 from IRQ stack to SVC stack
        STMFD   SP!, {R3-R10}
        STMFD   SP!, {R2}                           ; Push task's CPSR (i.e. IRQ's SPSR)
        bl      sys_enterInterrupt                  ; Start tracing the layers the interrupt has nested
    MEND

    MACRO
$Label  RESTORE_IRQ_CONTEXT
        MSR     CPSR_c, #(NO_INT | SYS32_MODE)      ; Disable interrupt
        bl      sys_leaveInterrupt                  ; Leave tracing and prepare quit
        mov     r0,sp                           
        add     sp,r0,#64                       
        LDR     LR, [SP, #-8]                       ; Manually restore register sp and lr in SYS32 mode,
                                                    ; for the registers sp & lr are different in SYS32 mode
                                                    ; from that in SVC32 mode
        MSR     CPSR_c, #(NO_INT | SVC32_MODE)      
        mov     sp, r0
        LDMFD   SP!, {r0}                           ; Pop new task's CPSR
        MSR     SPSR_cxsf, r0   
        LDMFD   SP!, {R0-R12,LR,pc}^                ; Pop new task's context
    MEND


;**************************************************************************************************
; Reset
;**************************************************************************************************
bt_reset
    ldr	    r0,=WTCON	    ;Disable WatchDog
    ldr	    r1,=0x0 		
    str	    r1,[r0]

    ;禁止所有中断
    ldr	    r0,=INTMSK
    ldr	    r1,=0x07ffffff  
    str	    r1,[r0]

    ;以下三段设置时钟控制寄存器
    ldr		r0,=LOCKTIME
    ldr		r1,=0xfff
    str		r1,[r0]

    IF PLLONSTART
    ldr		r0,=PLLCON			         ;锁相环倍频设定
    ldr		r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV)	 ;设定系统主时钟频率, Fin=8MHz,Fout=64MHz
    str		r1,[r0]
    ENDIF

    ldr	    r0,=CLKCON		 
    ldr	    r1,=0x7ff8	    ;所有功能单元块时钟使能
    str	    r1,[r0]

    ;为BDMA设置复位值