atmel_reg.h

CMX990 demonstration board (DE9901)

/****h* DE9901/ATMELREG
* FILE NAME
*  atmel_reg.h
* COPYRIGHT
*  (c) 2004-2005 Mobitex Technology AB - All rights reserved
* 
*  Redistribution and use in source and binary forms, with or without modification,
*  are permitted provided that the following conditions are met:
*  * 1. Redistributions of source code must retain the above copyright notice,
*       this list of conditions and the following disclaimer. 
*  * 2. Redistributions in binary form must reproduce the above copyright notice,
*       this list of conditions and the following disclaimer in the documentation
*       and/or other materials provided with the distribution.
*  * 3. The name Mobitex Technology AB may not be used to endorse or promote products
*       derived from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY MOBITEX TECHNOLOGY AB "AS IS" AND ANY EXPRESS OR
*  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
*  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
*  SHALL MOBITEX TECHNOLOGY AB BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
*  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
*  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
*  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
*  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* AUTHOR
*  MPN/Kjell Westerberg
* HISTORY
*  Changes in the file are recorded in this list.
*   Ver:  Date:       Responsible:         Comment:
*   R1A01 2005-01-17  Kjell Westerberg     Approved.
*   R1A05 2005-03-17  Kjell Westerberg     Added TC1.
* DESCRIPTION
*  This file defines some register and the memory map for the CPU.
***/

#ifndef ATMEL_REG_H_
#define ATMEL_REG_H_

#include "base_types.h"

/****d* ATMELREG/MCK
 * DESCRIPTION
 * CPU clock speed. Same as the reference clock.
 * It is defined in eCos with the constant CYGNUM_HAL_ARM_AT91_CLOCK_SPEED.
***/
#define MCK                     CYGNUM_HAL_ARM_AT91_CLOCK_SPEED

/****d* ATMELREG/MemoryMap
* DESCRIPTION
* Base address and length of different memory.
* SOURCE
*/
#define FLASH_BASE_ADDR        0x01000000     /* FLASH base.   */
#define FLASH_LEN              0x00200000     /* 2 Mbyte FLASH */

#define RAM_BASE_ADDR          0x00000000     /* RAM base.     */
#define RAM_LEN                0x00040000     /* 256 kB RAM    */

#define CMX_BASE               0x02000000     /* CMX990 chip base */
/***/

/****f* ATMELREG/IO
* DESCRIPTION
* Macros for accessing Atmel ARM CPU internal I/O registers.
* SOURCE
*/
#define OUTPUT(addr, value)   (*(volatile u8 *)(addr) = (value))
#define INPUT(addr)           (*(volatile u8 *)(addr))

#define OUTPUT32(addr, value) (*(volatile u32 *)(addr) = (value))
#define INPUT32(addr)         (*(volatile u32 *)(addr))
/***/

/****d* ATMELREG/PIO_
* DESCRIPTION
* Parallel I/O address definitions in the micro controller.
* SOURCE
*/
#define PIO_PER         (AT91_PIO + AT91_PIO_PER)
#define PIO_PDR         (AT91_PIO + AT91_PIO_PDR)
#define PIO_PSR         (AT91_PIO + AT91_PIO_PSR)
#define PIO_OER         (AT91_PIO + AT91_PIO_OER)
#define PIO_ODR         (AT91_PIO + AT91_PIO_ODR)
#define PIO_OSR         (AT91_PIO + AT91_PIO_OSR)
#define PIO_IFER        (AT91_PIO + AT91_PIO_IFER)
#define PIO_IFDR        (AT91_PIO + AT91_PIO_IFDR)
#define PIO_IFSR        (AT91_PIO + AT91_PIO_IFSR)
#define PIO_SODR        (AT91_PIO + AT91_PIO_SODR)
#define PIO_CODR        (AT91_PIO + AT91_PIO_CODR)
#define PIO_ODSR        (AT91_PIO + AT91_PIO_ODSR)
#define PIO_PDSR        (AT91_PIO + AT91_PIO_PDSR)
#define PIO_IER         (AT91_PIO + AT91_PIO_IER)
#define PIO_IDR         (AT91_PIO + AT91_PIO_IDR)
#define PIO_IMR         (AT91_PIO + AT91_PIO_IMR)
#define PIO_ISR         (AT91_PIO + AT91_PIO_ISR)
/***/

#define TC1_CCR         (AT91_TC + AT91_TC_TC1 + AT91_TC_CCR)
#define TC1_CMR         (AT91_TC + AT91_TC_TC1 + AT91_TC_CMR)
#define TC1_RC          (AT91_TC + AT91_TC_TC1 + AT91_TC_RC)
#define TC1_SR          (AT91_TC + AT91_TC_TC1 + AT91_TC_SR)
#define TC1_IER         (AT91_TC + AT91_TC_TC1 + AT91_TC_IER)
#define TC1_IDR         (AT91_TC + AT91_TC_TC1 + AT91_TC_IDR)

#endif /* ATMEL_REG_H */