energyw.h

一个电表的程序

#ifndef _ENERGY_H_
#define _ENERGY_H_
/*******************************************************************************
                Definition of Union ADE_REGS
*******************************************************************************/
//Data of this type are used for data exchange between ADE module and Core.
//It can be accessed in different methods:by byte,by word and by double word.
//So it provides an easy way to access the ADE registers.
typedef union
{
    unsigned long all;
    struct
    {
        unsigned int low;
        unsigned char high;
    }wordL;
    struct
    {
        unsigned char low;
        unsigned int  high;
    }wordH;
    struct
    {
        unsigned char DataL;
        unsigned char DataM;
        unsigned char DataH;
    }bytes;
}ADE_REGS;

typedef struct
{
 //  unsigned char DD;
 //  unsigned char MM;
 //  unsigned char YY;
   // unsigned char CF1;
  //  unsigned char PCF1;
    //unsigned char NCF1;
    unsigned long AE;
    unsigned long PAE;
    unsigned long NAE;
 //   unsigned char CF2;
 //   unsigned char PCF2;
  //  unsigned char NCF2;
    unsigned long RE;
    unsigned long PRE;
    unsigned long NRE;
  //  unsigned char Sum;
}EEDATA;
//这是一个独立开辟的区域
// 这里面有一个跨页的问题！！！！！

/******************************************************************************************/

__sfr __no_init volatile union
{
  unsigned char MIRQSTL;
  struct
  {
    unsigned char APNOLOAD : 1;
    unsigned char RNOLOAD : 1;
    unsigned char VANOLOAD : 1;
    unsigned char APSIGN : 1;
    unsigned char VARSIGN : 1;
    unsigned char FAULTSIGN : 1;
    unsigned char  : 1;
    unsigned char ADEIRQFLAG : 1;
  } MIRQSTL_bit;
} @ 0xDC;
/*******************************************************************************
                Definition of Energy Registers--MIRQSTL
*******************************************************************************/

  #define IF_ADEIRQ       0x80    //This bit is set if  any of ADE interrupt flags are set
  #define IF_FAULTSIGN    0x20    //Logic one indicates that the Fault mode has changed.
  #define IF_VARSIGN      0x10    //Logic one indicates that the reactive power sign changed.
  #define IF_APSIGN       0x08    //Logic one indicates that the active power sign changed.
  #define IF_VANOLOAD     0x04    //Logic one indicates that the apparent power no-load is detected.
  #define IF_RNOLOAD      0x02    //Logic one indicates that the reactive power no-load is detected.
  #define IF_APNOLOAD     0x01    //Logic one indicates that the active power no-load is detected.
/***************************************************************************************************/
__sfr __no_init volatile union
{
  unsigned char MIRQSTM;
  struct
  {
    unsigned char AEHF : 1;
    unsigned char REHF : 1;
    unsigned char VAEHF : 1;
    unsigned char AEOF : 1;
    unsigned char REOF : 1;
    unsigned char VAEOF : 1;
    unsigned char CF1 : 1;
    unsigned char CF2 : 1;
  } MIRQSTM_bit;
} @ 0xDD;
/*******************************************************************************
                Definition of Energy Registers--MIRQSTM
*******************************************************************************/

  #define IF_CF2          0x80    //Logic one indicates that a pulse of CF2 has been issued.
  #define IF_CF1          0x40    //Logic one indicates that a pulse of CF1 has been issued.
  #define IF_VAEOF        0x20    //Logic one indicates that the VAHR register has overflowded.
  #define IF_REOF         0x10    //Logic one indicates that the VARHR register has overflowded.
  #define IF_AEOF         0x08    //Logic one indicates that the WATTHR register has overflowded.
  #define IF_VAEHF        0x04    //Logic one indicates that the VAHR register is half full.
  #define IF_REHF         0x02    //Logic one indicates that the VARHR register is half full.
  #define IF_AEHF         0x01    //Logic one indicates that the WATTHR register is half full.
/***********************************************************************************************/
__sfr __no_init volatile union
{
  unsigned char MIRQSTH;
  struct
  {
    unsigned char ZX : 1;
    unsigned char ZXTO : 1;
    unsigned char CYCEND : 1;
    unsigned char PKV : 1;
    unsigned char PKI : 1;
    unsigned char WFSM : 1;
    unsigned char  : 1;
    unsigned char RESET : 1;
  } MIRQSTH_bit;
} @ 0xDE;
/*******************************************************************************
                Definition of Energy Registers--MIRQSTH
*******************************************************************************/

  #define IF_RESET        0x80    //Indicates the end of reset(for both software or hardware reset)
  #define IF_WFSM         0x20    //Indicates new data is present in the waveform register
  #define IF_PKI          0x10    //Indicates current channel has exceeded the IPKLVL value.
  #define IF_PKV          0x08    //Indicates voltage channel has exceeded the VPKLVL value.
  #define IF_CYCEND       0x04    //Indicates the end of the energy accumulation over an integer number
                                //of half line cycles.
  #define IF_ZXTO         0x02    //Indicates no zero crossing on the line voltage happened for the
                                //last ZXTOUT half line  cycles.
  #define IF_ZX           0x01    //Indicates detection of a zero crossing in the voltage channel.
/***************************************************************************************************/
__sfr __no_init volatile union
{
  unsigned char MIRQENL;
  struct
  {
    unsigned char APNOLOAD : 1;
    unsigned char RNOLOAD : 1;
    unsigned char VANOLOAD : 1;
    unsigned char APSIGN : 1;
    unsigned char VARSIGN : 1;
    unsigned char FAULTSIGN : 1;
    unsigned char  : 1;
    unsigned char  : 1;
  } MIRQENL_bit;
} @ 0xD9;
/*******************************************************************************
                Definition of Energy Registers--MIRQENL
*******************************************************************************/

  #define IE_FAULTSIGN    0x20    //1-the FAULTSIGN bit set creates a pending ADE interrupt.
  #define IE_VARSIGN      0x10    //1-the VARSIGN bit set creates a pending ADE interrupt.
  #define IE_APSIGN       0x08    //1-the APSIGN bit set creates a pending ADE interrupt.
  #define IE_VANOLOAD     0x04    //1-the VANOLOAD bit set creates a pending ADE interrupt
  #define IE_RNOLOAD      0x02    //1-the RNOLOAD bit set creates a pending ADE interrupt
  #define IE_APNOLOAD     0x01    //1-the APNOLOAD bit set creates a pending ADE interrupt
/***************************************************************************************/
__sfr __no_init volatile union
{
  unsigned char MIRQENM;
  struct
  {
    unsigned char AEHF : 1;
    unsigned char REHF : 1;
    unsigned char VAEHF : 1;
    unsigned char AEOF : 1;
    unsigned char REOF : 1;
    unsigned char VAEOF : 1;
    unsigned char CF1 : 1;
    unsigned char CF2 : 1;
  } MIRQENM_bit;
} @ 0xDA;
/*******************************************************************************
                Definition of Energy Registers--MIRQENM
*******************************************************************************/
#define MIRQENM
#define IE_CF2          0x80    //1-a CF2 pulse issued creates a pending ADE interrupt
#define IE_CF1          0x40    //1-a CF1 pulse issued creates a pending ADE interrupt
#define IE_VAEOF        0x20    //1-the VAEOF flag set creates a pending ADE interrupt
#define IE_REOF         0x10    //1-the REOF flag set creates a pending ADE interrupt
#define IE_AEOF         0x08    //1-the AEOF flag set creates a pending ADE interrupt
#define IE_VAEHF        0x04    //1-the VAEHF flag set creates a pending ADE interrupt
#define IE_REHF         0x02    //1-the REHF flag set creates a pending ADE interrupt
#define IE_AEHF         0x01    //1-the AEHF flag set creates a pending ADE interrupt
/*****************************************************************************************/
__sfr __no_init volatile union
{
  unsigned char MIRQENH;
  struct
  {
    unsigned char ZX : 1;
    unsigned char ZXTO : 1;
    unsigned char CYCEND : 1;
    unsigned char PKV : 1;
    unsigned char PKI : 1;
    unsigned char WFSM : 1;
    unsigned char  : 1;
    unsigned char  : 1;
  } MIRQENH_bit;
} @ 0xDB;
/*******************************************************************************
                Definition of Energy Registers--MIRQENH
*******************************************************************************/
#define IE_WFSM         0x20    //1-the WFSM flag set creates a pending ADE interrupt
#define IE_PKI          0x10    //1-the PKI flag set creates a pending ADE interrupt
#define IE_PKV          0x08    //1-the PKV flag set creates a pending ADE interrupt
#define IE_CYCEND       0x04    //1-the CYCEND flag set creates a pending ADE interrupt
#define IE_ZXTO         0x02    //1-the ZXTO flag set creates a pending ADE interrupt
#define IE_ZX           0x01    //1-the ZX flag set creates a pending ADE interrupt
/******************************************************************************************/
__sfr __no_init volatile unsigned char MADDPT @ 0x91;
__sfr __no_init volatile unsigned char MDATL @ 0x92;
__sfr __no_init volatile unsigned char MDATM @ 0x93;
__sfr __no_init volatile unsigned char MDATH @ 0x94;
__sfr __no_init volatile unsigned char WAV1L @ 0xE2;
__sfr __no_init volatile unsigned char VRMSL @ 0xD1;
__sfr __no_init volatile unsigned char VRMSM @ 0xD2;
__sfr __no_init volatile unsigned char VRMSH @ 0xD3;
__sfr __no_init volatile unsigned char IRMSL @ 0xD4;
__sfr __no_init volatile unsigned char IRMSM @ 0xD5;
__sfr __no_init volatile unsigned char IRMSH @ 0xD6;
__sfr __no_init volatile unsigned char WAV1M @ 0xE3;
__sfr __no_init volatile unsigned char WAV1H @ 0xE4;
__sfr __no_init volatile unsigned char WAV2L @ 0xE5;
__sfr __no_init volatile unsigned char WAV2M @ 0xE6;
__sfr __no_init volatile unsigned char WAV2H @ 0xE7;

//the following registers can be accessed using MADDPT and MDAT SFRs
//For this reason they are declared with #define
#define WATTHR    0x01
#define RWATTHR   0x02
#define LWATTHR   0x03
#define VARHR     0x04
#define RVARHR    0x05
#define LVARHR    0x06
#define VAHR      0x07
#define RVAHR     0x08
#define LVAHR     0x09
#define PER_FREQ  0x0A

#define PHCAL     0x10
#define ZXTOUT    0x11
#define LINCYC    0x12
#define SAGCYC    0x13
#define SAGLVL    0x14
#define IPKLVL    0x15
#define VPKLVL    0x16
#define IPEAK     0x17
#define RSTIPEAK  0x18
#define VPEAK     0x19
#define RSTVPEAK  0x1A
#define IBGAIN  0x1C