initialize.c

dsp的设计

//==========PLL initialize routine=======

void ini_pll(void)
{
	CLKMD=(1<<CLKMD0);							//X2/CLKIN is selected as clock input source. set GPIO4 is high at reset.
	
	PLLCSR=(1<<PLLRST);							//PLLEN = 0:bypass mode.PLLRST=1:set PLL to reset state 
	PLLM=(1<<PLLM3)|(1<<PLLM2)|(1<<PLLM1)|(1<<PLLM0);						//PLLM=01111,multiplier=15
	PLLDIV0=(1<<PLLDIV00);																			//PLLDIV0 = 00001: Divide by 2
																															//40M*(15/2)=300MHz
	delay1us();
	PLLCSR&=~(1<<PLLRST);						//Release the PLL from its reset state by setting PLLRST to 0.
	
	while(1)												//Wait for the PLL to relock by polling the LOCK bit
	{
		if(PLLCSR&(1<<LOCK))
			break;			
	}
																																
	PLLCSR=(1<<PLLEN);							//Switch back to PLL mode by setting the PLLEN bit to 1.
																															
	CK3SEL=(1<<CK3SEL3)|(1<<CK3SEL1)|(1<<CK3SEL0);							//CLKOUT3 becomes point C in Figure 3-14	5502datasheet P52	
																															//CPU core clock=CLKOUT3=300MHz
																															
	PLLDIV1=(1<<PLLDIV11)|(1<<PLLDIV10);												//PLLDIV1 = 00000: Divide by 1;00001: Divide by 2;00011: Divide by 4
																															//Fast Peripherals(DMA\HPI\TIMER) Clock Group=300/4=75MHz
																															
	PLLDIV2=(1<<PLLDIV21)|(1<<PLLDIV20);												//Slow Peripherals(McBSPs\I2C\UART) Clock Group=300/4=75MHz		
	
	PLLDIV3=(1<<PLLDIV31)|(1<<PLLDIV30);												//External Memory Interface Clock Group=300/4=75MHz
																															//SDRAM:W9864G2EH-6,speed up to 166MHz
																															//set EMIFCLKS pin low,EMIF will be clocked via the same internal clock	
	
																	
}
//

//==========timer0 initialize routine=======
 
//Interrupts remain disabled until the stack pointers
//are initialized by a software write to each pointer (the SP and SSP
//registers). After stack initialization, the INTM bit and the IER0 and IER1
//registers determine interrupt enabling.

extern unsigned long int  VECSTART;		//declare interrupt vector table address defined in vectors.asm
void ini_timer0(void)
{
	asm(" BCLR C54CM");
	asm(" BSET INTM");													//INTM=0:All unmasked interrupts are enabled.
	IVPD=((unsigned long int )&VECSTART)>>8;		//initialize these registers before globally enabling 
	IVPH=((unsigned long int )&VECSTART)>>8;		//(INTM = 0) the maskable interrupts.

													

	GPTGPEN_0=0;						//timer functionality not GPIO mode
	TSSR=(1<<TIM0_MODE);		//TIM0 pin is used as the timer output pin.

	GPTCNT1_0=0;
	GPTCNT2_0=0;
	GPTCNT3_0=0;
	GPTCNT4_0=0;
	
	GPTPRD1_0=0x100;
	GPTPRD2_0=0;
	GPTPRD3_0=0;
	GPTPRD4_0=0;
	
	GPTGCTL1_0=(1<<TIM34RS)|(1<<TIM12RS);		//The timer is in the 64-bit general-purpose timer mode.
	GPTCTL1_0=(1<<ENAMODE1);		//The clock source is the internal clock.
															//The timer is enabled continuously.
 	asm(" BCLR INTM");
	IER0=(1<<TINT0);						//enable timer0 interruptInitialize
}

//==========xxx initialize routine=======