osplatform.h

osapi 2.0 操作系统抽象层 "系统抽象层"使得你可以实现一种对于RTOS、CPU和所运行产品物理特性完全透明的软件。使用这种公共通用接口

/*
** osplatform.h
**
*/

#ifndef _osplatform_
#define _osplatform_

/*
** MET defines
*/
/* Unused heritage (these three) */
#define MET_SUBSECS_SW_TRIGGER      0x70000000
#define MET_LATCH_HIGH32_TIME       0x70000004
#define MET_LATCH_LOW32_TIME        0x70000008

/* Real SDN registers */
#define SDN_MET_SW_LATCH_REG        0xE0000300
#define SDN_MET_SW_HIGH32_REG       0xE0000304
#define SDN_MET_SW_LOW32_REG        0xE0000308
#define SDN_MET_1553_HIGH32_REG     0xE000030C
#define SDN_MET_1553_LOW32_REG      0xE0000310
#define SDN_MET_ASD_HIGH32_REG      0xE0000314
#define SDN_MET_ASD_LOW32_REG       0xE0000318
#define SDN_MET_TEST_HIGH32_REG     0xE000031C
#define SDN_MET_TEST_LOW32_REG      0xE0000320

/* Generic Label for Test registers */
#define TIME_TEST_HIGH32_REG    SDN_MET_TEST_HIGH32_REG
#define TIME_TEST_LOW32_REG     SDN_MET_TEST_LOW32_REG

#define SDN_WATCHDOG_ENABLE_REG     0xE0000100
#define SDN_WATCHDOG_STATUS_REG     0xE0000104
#define SDN_WATCHDOG_ACK_REG        0xE0000108
#define SDN_WATCHDOG_TIMEOUT_REG    0xE000010C

/*
** These are the base physical memory addresses for the DDC Shared Ram and Registers
*/
#define  DDC_MEM_BASE_ADDR           0x90008000
#define  DDC_REG_BASE_ADDR           0x90000000

/*
** Defines for interrupts
*/

/* 1553 interrupt vector is AVEC3 on SDN prototype board */
/* See bsp.h in compiler toolchain for details */

#define OS_1553_INT_VECTOR          (27)

/* 
** Interrupt bit assignments for the 5208/sdn 
*/
#define RHCF5208_INTR_DMA_3   (17)                                                                    
#define RHCF5208_INTR_DMA_2   (16)                                                                    
#define RHCF5208_INTR_DMA_1   (15)
#define RHCF5208_INTR_DMA_0   (14)                                                                    
#define RHCF5208_INTR_UART_2  (13)                                                                    
#define RHCF5208_INTR_UART_1  (12)
#define RHCF5208_INTR_MBUS    (11)                                                                    
#define RHCF5208_INTR_TIMER_2 (10)                                                                    
#define RHCF5208_INTR_TIMER_1 (9)                                                                     
#define RHCF5208_INTR_SWT     (8)
#define RHCF5208_INTR_EINT7   (7)                                                                     
#define RHCF5208_INTR_EINT6   (6)                                                                     
#define RHCF5208_INTR_EINT5   (5)                                                                     
#define RHCF5208_INTR_EINT4   (4)                                                                     
#define RHCF5208_INTR_EINT3   (3)                                                                     
#define RHCF5208_INTR_EINT2   (2)
#define RHCF5208_INTR_EINT1   (1)     

/*
** Address ranges for all memory banks.
*/

#define OS_MAX_MEMORY_BANKS            4

#define OS_SRAM_BANK_START_ADDRESS     0x20000000
#define OS_SRAM_BANK_END_ADDRESS       0x2007FFFF

#define OS_EEPROM1_BANK_START_ADDRESS  0x50000000
#define OS_EEPROM1_BANK_END_ADDRESS    0x500FFFFF

#define OS_EEPROM2_BANK_START_ADDRESS  0x50100000
#define OS_EEPROM2_BANK_END_ADDRESS    0x501FFFFF

#define OS_PROM_BANK_START_ADDRESS     0xFFE00000
#define OS_PROM_BANK_END_ADDRESS       0xFFE0FFFF

#define OS_EEPROM_CHECKSUM_ADDRESS     0xFFFFFFFF  /* bogus address for now*/

/*
** EEPROM characteristic
*/
#define OS_EEPROM_WRITE_DELAY          20 /* time required for the EEPROM to write itself */


#endif