specctra.did

candence工程文件

# Cadence Design Systems, Inc.
# Allegro PCB Router Automatic Router
# Allegro PCB Router V15.7 made 2006/05/31 at 22:07:34
# Running on host 
# 
#            Command Line Parameters
#            -----------------------
# Design File Name : D:/老于/PCB工程文件/unrouted\DSPsystem.dsn
# Initialization options:
#   -do pasde.do
# Status File Name : D:/老于/PCB工程文件/unrouted\monitor.sts
# -nog specified. Graphics not utilized.
# Use Colormap In Design File.
#
#
#
#
# do $/DSPsystem_rules.do
rule PCB (width 8)
rule PCB (clearance 8 (type wire_wire))
rule PCB (clearance 8 (type wire_smd))
rule PCB (clearance 8 (type wire_pin))
rule PCB (clearance 8 (type wire_via))
rule PCB (clearance 6 (type smd_smd))
rule PCB (clearance 6 (type smd_pin))
rule PCB (clearance 8 (type smd_via))
rule PCB (clearance 6 (type pin_pin))
rule PCB (clearance 8 (type pin_via))
rule PCB (clearance 8 (type via_via))
rule PCB (clearance 8 (type test_test))
rule PCB (clearance 8 (type test_wire))
rule PCB (clearance 8 (type test_smd))
rule PCB (clearance 8 (type test_pin))
rule PCB (clearance 8 (type test_via))
rule PCB (clearance 5 (type buried_via_gap))
rule PCB (clearance 0 (type area_wire))
rule PCB (clearance 0 (type area_smd))
rule PCB (clearance 0 (type area_area))
rule PCB (clearance 0 (type area_pin))
rule PCB (clearance 0 (type area_via))
rule PCB (clearance 0 (type area_test))
rule pcb (tjunction on)(junction_type all)
rule pcb (staggered_via on (min_gap 5)(max_gap -0.001))
rule layer TOP (restricted_layer_length_factor 1)
rule layer BOTTOM (restricted_layer_length_factor 1)
write colormap _notify.std
# do C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaac03496.tmp
unselect all routing
set route_diagonal 0
grid wire 1.000000 (direction x) (offset 0.000000)
grid wire 1.000000 (direction y) (offset 0.000000)
grid via 1.000000 (direction x) (offset 0.000000)
grid via 1.000000 (direction y) (offset 0.000000)
protect all wires
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
cost via -1
set turbo_stagger off
limit outside -1
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
unprotect selected
# do D:/老于/PCB工程文件/unrouted/pasde.do
# do $/DSPsystem_rules.do
rule PCB (width 8)
rule PCB (clearance 8 (type wire_wire))
rule PCB (clearance 8 (type wire_smd))
rule PCB (clearance 8 (type wire_pin))
rule PCB (clearance 8 (type wire_via))
rule PCB (clearance 6 (type smd_smd))
rule PCB (clearance 6 (type smd_pin))
rule PCB (clearance 8 (type smd_via))
rule PCB (clearance 6 (type pin_pin))
rule PCB (clearance 8 (type pin_via))
rule PCB (clearance 8 (type via_via))
rule PCB (clearance 8 (type test_test))
rule PCB (clearance 8 (type test_wire))
rule PCB (clearance 8 (type test_smd))
rule PCB (clearance 8 (type test_pin))
rule PCB (clearance 8 (type test_via))
rule PCB (clearance 5 (type buried_via_gap))
rule PCB (clearance 0 (type area_wire))
rule PCB (clearance 0 (type area_smd))
rule PCB (clearance 0 (type area_area))
rule PCB (clearance 0 (type area_pin))
rule PCB (clearance 0 (type area_via))
rule PCB (clearance 0 (type area_test))
rule pcb (tjunction on)(junction_type all)
rule pcb (staggered_via on (min_gap 5)(max_gap -0.001))
rule layer TOP (restricted_layer_length_factor 1)
rule layer BOTTOM (restricted_layer_length_factor 1)
write colormap _notify.std
write routes (changed_only) (reset_changed) C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaad03496.tmp
# do C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaae03496.tmp
unselect all routing
set route_diagonal 0
grid wire 1.000000 (direction x) (offset 0.000000)
grid wire 1.000000 (direction y) (offset 0.000000)
grid via 1.000000 (direction x) (offset 0.000000)
grid via 1.000000 (direction y) (offset 0.000000)
protect all wires
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
cost via -1
set turbo_stagger off
limit outside -1
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
unprotect selected
# do D:/老于/PCB工程文件/unrouted/pasde.do
# do $/DSPsystem_rules.do
rule PCB (width 8)
rule PCB (clearance 8 (type wire_wire))
rule PCB (clearance 8 (type wire_smd))
rule PCB (clearance 8 (type wire_pin))
rule PCB (clearance 8 (type wire_via))
rule PCB (clearance 6 (type smd_smd))
rule PCB (clearance 6 (type smd_pin))
rule PCB (clearance 8 (type smd_via))
rule PCB (clearance 6 (type pin_pin))
rule PCB (clearance 8 (type pin_via))
rule PCB (clearance 8 (type via_via))
rule PCB (clearance 8 (type test_test))
rule PCB (clearance 8 (type test_wire))
rule PCB (clearance 8 (type test_smd))
rule PCB (clearance 8 (type test_pin))
rule PCB (clearance 8 (type test_via))
rule PCB (clearance 5 (type buried_via_gap))
rule PCB (clearance 0 (type area_wire))
rule PCB (clearance 0 (type area_smd))
rule PCB (clearance 0 (type area_area))
rule PCB (clearance 0 (type area_pin))
rule PCB (clearance 0 (type area_via))
rule PCB (clearance 0 (type area_test))
rule pcb (tjunction on)(junction_type all)
rule pcb (staggered_via on (min_gap 5)(max_gap -0.001))
rule layer TOP (restricted_layer_length_factor 1)
rule layer BOTTOM (restricted_layer_length_factor 1)
write colormap _notify.std
write routes (changed_only) (reset_changed) C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaaf03496.tmp
# do C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaag03496.tmp
unselect all routing
set route_diagonal 0
grid wire 1.000000 (direction x) (offset 0.000000)
grid wire 1.000000 (direction y) (offset 0.000000)
grid via 1.000000 (direction x) (offset 0.000000)
grid via 1.000000 (direction y) (offset 0.000000)
protect all wires
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
cost via -1
set turbo_stagger off
limit outside -1
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
unprotect selected
# do D:/老于/PCB工程文件/unrouted/pasde.do
# do $/DSPsystem_rules.do
rule PCB (width 8)
rule PCB (clearance 8 (type wire_wire))
rule PCB (clearance 8 (type wire_smd))
rule PCB (clearance 8 (type wire_pin))
rule PCB (clearance 8 (type wire_via))
rule PCB (clearance 6 (type smd_smd))
rule PCB (clearance 6 (type smd_pin))
rule PCB (clearance 8 (type smd_via))
rule PCB (clearance 6 (type pin_pin))
rule PCB (clearance 8 (type pin_via))
rule PCB (clearance 8 (type via_via))
rule PCB (clearance 8 (type test_test))
rule PCB (clearance 8 (type test_wire))
rule PCB (clearance 8 (type test_smd))
rule PCB (clearance 8 (type test_pin))
rule PCB (clearance 8 (type test_via))
rule PCB (clearance 5 (type buried_via_gap))
rule PCB (clearance 0 (type area_wire))
rule PCB (clearance 0 (type area_smd))
rule PCB (clearance 0 (type area_area))
rule PCB (clearance 0 (type area_pin))
rule PCB (clearance 0 (type area_via))
rule PCB (clearance 0 (type area_test))
rule pcb (tjunction on)(junction_type all)
rule pcb (staggered_via on (min_gap 5)(max_gap -0.001))
rule layer TOP (restricted_layer_length_factor 1)
rule layer BOTTOM (restricted_layer_length_factor 1)
write colormap _notify.std
write routes (changed_only) (reset_changed) C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaah03496.tmp
# do C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaai03496.tmp
unselect all routing
set route_diagonal 0
grid wire 1.000000 (direction x) (offset 0.000000)
grid wire 1.000000 (direction y) (offset 0.000000)
grid via 1.000000 (direction x) (offset 0.000000)
grid via 1.000000 (direction y) (offset 0.000000)
protect all wires
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
cost via -1
set turbo_stagger off
limit outside -1
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
unprotect selected
# do D:/老于/PCB工程文件/unrouted/pasde.do
# do $/DSPsystem_rules.do
rule PCB (width 8)
rule PCB (clearance 8 (type wire_wire))
rule PCB (clearance 8 (type wire_smd))
rule PCB (clearance 8 (type wire_pin))
rule PCB (clearance 8 (type wire_via))
rule PCB (clearance 6 (type smd_smd))
rule PCB (clearance 6 (type smd_pin))
rule PCB (clearance 8 (type smd_via))
rule PCB (clearance 6 (type pin_pin))
rule PCB (clearance 8 (type pin_via))
rule PCB (clearance 8 (type via_via))
rule PCB (clearance 8 (type test_test))
rule PCB (clearance 8 (type test_wire))
rule PCB (clearance 8 (type test_smd))
rule PCB (clearance 8 (type test_pin))
rule PCB (clearance 8 (type test_via))
rule PCB (clearance 5 (type buried_via_gap))
rule PCB (clearance 0 (type area_wire))
rule PCB (clearance 0 (type area_smd))
rule PCB (clearance 0 (type area_area))
rule PCB (clearance 0 (type area_pin))
rule PCB (clearance 0 (type area_via))
rule PCB (clearance 0 (type area_test))
rule pcb (tjunction on)(junction_type all)
rule pcb (staggered_via on (min_gap 5)(max_gap -0.001))
rule layer TOP (restricted_layer_length_factor 1)
rule layer BOTTOM (restricted_layer_length_factor 1)
write colormap _notify.std
write routes (changed_only) (reset_changed) C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaaj03496.tmp
# do C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/#Taaaaak03496.tmp
unselect all routing
set route_diagonal 0
grid wire 1.000000 (direction x) (offset 0.000000)
grid wire 1.000000 (direction y) (offset 0.000000)