controll.vhd

用VHDL语言描述十六路彩灯的设计其开发均在FPGA中

LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE state_pack IS
TYPE state IS (Qa,Qb,Qc,Qd,Qe,Qf,Qg);
END state_pack;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.state_pack.all;

ENTITY controll IS
PORT(K,S,Qcl,Qc2,CLK:IN std_logic;
Y,K1,K2,K3,K4,K5,K6:OUT std_logic);
END controll;

ARCHITECTURE controll_arc OF controll IS
SIGNAL current_state:state:=Qa;

BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1'AND CLK'EVENT;
IF S='0'THEN
  Y<='0';
ELSE
  Y<='1';
END IF;
IF K<='0' THEN
  K1<='0';K2<='0';K3<='1';
  K4<='1';K5<='1';K6<='1';
  current_state<=Qa;
ELSE
  CASE current_state IS
WHEN Qa=>
  current_state<=Qb;
  K1<='1' ;K3<='0' ;
WHEN Qb=>
  IF Qcl<='0' THEN current_state<=Qb;
ELSE
  current_state<=Qc;
  K1<='0' ;K2<='1' ;
END IF;
WHEN Qc=>
  IF Qc2<='0' THEN
  current_state<=Qc;
ELSE
  current_state<=Qd;
  K4<='0';
END IF;
WHEN Qd=>
  IF Qc2<='0' THEN
  current_state<=Qd;
ELSE
  current_state<=Qe;
  K1<='1' ;K2<='0';
END IF;
WHEN Qe=>
  IF Qcl<='0' THEN
  current_state<=Qe;
ELSE
  current_state<=Qf;
  K4<='1' ;K6<='0' ;
END IF;
WHEN Qf=>
  IF Qcl<='0' THEN
  current_state<=Qf;
ELSE
  K1<='0';K2<='1';K3<='1';
  K5<='0';K6<='1';
  current_state<=Qg;
END IF;
WHEN Qg=>
  IF Qc2<='0'THEN
  current_state<=Qg;
ELSE
  current_state<=Qa;
  K1<='0';K2<='0';K3<='1';
  K4<='1';K5<='1';K6<='1';
END IF;
END CASE;
END IF;
END PROCESS;
END controll_arc;