📄 controll.tan.rpt
字号:
; N/A ; None ; 4.911 ns ; Qcl ; K5~reg0 ; CLK ;
; N/A ; None ; 4.823 ns ; Qcl ; current_state.qe ; CLK ;
; N/A ; None ; 4.794 ns ; K ; current_state.qe ; CLK ;
; N/A ; None ; 4.794 ns ; K ; current_state.qd ; CLK ;
; N/A ; None ; 4.792 ns ; K ; K2~reg0 ; CLK ;
; N/A ; None ; 4.749 ns ; K ; current_state.qg ; CLK ;
; N/A ; None ; 4.748 ns ; K ; current_state.qa ; CLK ;
; N/A ; None ; 4.694 ns ; Qc2 ; current_state.qc ; CLK ;
; N/A ; None ; 4.636 ns ; Qcl ; current_state.qg ; CLK ;
; N/A ; None ; 4.630 ns ; K ; current_state.qc ; CLK ;
; N/A ; None ; 4.573 ns ; Qcl ; K3~reg0 ; CLK ;
; N/A ; None ; 4.560 ns ; Qc2 ; current_state.qe ; CLK ;
; N/A ; None ; 4.559 ns ; Qc2 ; current_state.qd ; CLK ;
; N/A ; None ; 4.486 ns ; Qc2 ; current_state.qa ; CLK ;
; N/A ; None ; 4.484 ns ; Qc2 ; current_state.qg ; CLK ;
; N/A ; None ; 4.386 ns ; K ; current_state.qb ; CLK ;
; N/A ; None ; 4.331 ns ; Qcl ; current_state.qc ; CLK ;
; N/A ; None ; 4.331 ns ; Qcl ; current_state.qb ; CLK ;
; N/A ; None ; 4.326 ns ; Qcl ; K4~reg0 ; CLK ;
; N/A ; None ; 4.324 ns ; Qcl ; current_state.qf ; CLK ;
; N/A ; None ; 3.870 ns ; S ; Y~reg0 ; CLK ;
+-------+--------------+------------+------+------------------+----------+
+---------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A ; None ; 7.758 ns ; K5~reg0 ; K5 ; CLK ;
; N/A ; None ; 7.137 ns ; K4~reg0 ; K4 ; CLK ;
; N/A ; None ; 6.996 ns ; K3~reg0 ; K3 ; CLK ;
; N/A ; None ; 6.984 ns ; K2~reg0 ; K2 ; CLK ;
; N/A ; None ; 6.972 ns ; K1~reg0 ; K1 ; CLK ;
; N/A ; None ; 6.548 ns ; K6~reg0 ; K6 ; CLK ;
; N/A ; None ; 6.270 ns ; Y~reg0 ; Y ; CLK ;
+-------+--------------+------------+---------+----+------------+
+------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+------------------+----------+
; N/A ; None ; -3.818 ns ; S ; Y~reg0 ; CLK ;
; N/A ; None ; -4.272 ns ; Qcl ; current_state.qf ; CLK ;
; N/A ; None ; -4.274 ns ; Qcl ; K4~reg0 ; CLK ;
; N/A ; None ; -4.279 ns ; Qcl ; current_state.qc ; CLK ;
; N/A ; None ; -4.279 ns ; Qcl ; current_state.qb ; CLK ;
; N/A ; None ; -4.334 ns ; K ; current_state.qb ; CLK ;
; N/A ; None ; -4.432 ns ; Qc2 ; current_state.qg ; CLK ;
; N/A ; None ; -4.434 ns ; Qc2 ; current_state.qa ; CLK ;
; N/A ; None ; -4.507 ns ; Qc2 ; current_state.qd ; CLK ;
; N/A ; None ; -4.508 ns ; Qc2 ; current_state.qe ; CLK ;
; N/A ; None ; -4.521 ns ; Qcl ; K3~reg0 ; CLK ;
; N/A ; None ; -4.578 ns ; K ; current_state.qc ; CLK ;
; N/A ; None ; -4.584 ns ; Qcl ; current_state.qg ; CLK ;
; N/A ; None ; -4.642 ns ; Qc2 ; current_state.qc ; CLK ;
; N/A ; None ; -4.696 ns ; K ; current_state.qa ; CLK ;
; N/A ; None ; -4.697 ns ; K ; current_state.qg ; CLK ;
; N/A ; None ; -4.740 ns ; K ; K2~reg0 ; CLK ;
; N/A ; None ; -4.742 ns ; K ; current_state.qe ; CLK ;
; N/A ; None ; -4.742 ns ; K ; current_state.qd ; CLK ;
; N/A ; None ; -4.771 ns ; Qcl ; current_state.qe ; CLK ;
; N/A ; None ; -4.859 ns ; Qcl ; K5~reg0 ; CLK ;
; N/A ; None ; -4.941 ns ; K ; current_state.qf ; CLK ;
; N/A ; None ; -5.107 ns ; Qc2 ; K4~reg0 ; CLK ;
; N/A ; None ; -5.108 ns ; Qcl ; K6~reg0 ; CLK ;
; N/A ; None ; -5.144 ns ; Qc2 ; K2~reg0 ; CLK ;
; N/A ; None ; -5.245 ns ; Qcl ; K1~reg0 ; CLK ;
; N/A ; None ; -5.374 ns ; Qc2 ; K1~reg0 ; CLK ;
; N/A ; None ; -5.512 ns ; Qcl ; K2~reg0 ; CLK ;
; N/A ; None ; -5.581 ns ; Qc2 ; K3~reg0 ; CLK ;
; N/A ; None ; -5.805 ns ; K ; K3~reg0 ; CLK ;
; N/A ; None ; -5.822 ns ; Qc2 ; K5~reg0 ; CLK ;
; N/A ; None ; -5.829 ns ; Qc2 ; K6~reg0 ; CLK ;
; N/A ; None ; -6.046 ns ; K ; K5~reg0 ; CLK ;
; N/A ; None ; -6.053 ns ; K ; K6~reg0 ; CLK ;
; N/A ; None ; -6.054 ns ; K ; K4~reg0 ; CLK ;
; N/A ; None ; -6.259 ns ; K ; K1~reg0 ; CLK ;
+---------------+-------------+-----------+------+------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Thu Jun 21 18:27:37 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off controll -c controll --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "current_state.qg" and destination register "K1~reg0"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 3.264 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y10_N4; Fanout = 8; REG Node = 'current_state.qg'
Info: 2: + IC(1.139 ns) + CELL(0.292 ns) = 1.431 ns; Loc. = LC_X1_Y10_N2; Fanout = 1; COMB Node = 'K1~226'
Info: 3: + IC(1.095 ns) + CELL(0.738 ns) = 3.264 ns; Loc. = LC_X2_Y10_N3; Fanout = 4; REG Node = 'K1~reg0'
Info: Total cell delay = 1.030 ns ( 31.56 % )
Info: Total interconnect delay = 2.234 ns ( 68.44 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLK" to destination register is 2.767 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'
Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y10_N3; Fanout = 4; REG Node = 'K1~reg0'
Info: Total cell delay = 2.180 ns ( 78.79 % )
Info: Total interconnect delay = 0.587 ns ( 21.21 % )
Info: - Longest clock path from clock "CLK" to source register is 2.767 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'
Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X3_Y10_N4; Fanout = 8; REG Node = 'current_state.qg'
Info: Total cell delay = 2.180 ns ( 78.79 % )
Info: Total interconnect delay = 0.587 ns ( 21.21 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "K1~reg0" (data pin = "K", clock pin = "CLK") is 6.311 ns
Info: + Longest pin to register delay is 9.041 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 10; PIN Node = 'K'
Info: 2: + IC(5.149 ns) + CELL(0.590 ns) = 7.208 ns; Loc. = LC_X1_Y10_N2; Fanout = 1; COMB Node = 'K1~226'
Info: 3: + IC(1.095 ns) + CELL(0.738 ns) = 9.041 ns; Loc. = LC_X2_Y10_N3; Fanout = 4; REG Node = 'K1~reg0'
Info: Total cell delay = 2.797 ns ( 30.94 % )
Info: Total interconnect delay = 6.244 ns ( 69.06 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "CLK" to destination register is 2.767 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'
Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y10_N3; Fanout = 4; REG Node = 'K1~reg0'
Info: Total cell delay = 2.180 ns ( 78.79 % )
Info: Total interconnect delay = 0.587 ns ( 21.21 % )
Info: tco from clock "CLK" to destination pin "K5" through register "K5~reg0" is 7.758 ns
Info: + Longest clock path from clock "CLK" to source register is 2.767 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'
Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X3_Y10_N2; Fanout = 2; REG Node = 'K5~reg0'
Info: Total cell delay = 2.180 ns ( 78.79 % )
Info: Total interconnect delay = 0.587 ns ( 21.21 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 4.767 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y10_N2; Fanout = 2; REG Node = 'K5~reg0'
Info: 2: + IC(2.659 ns) + CELL(2.108 ns) = 4.767 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'K5'
Info: Total cell delay = 2.108 ns ( 44.22 % )
Info: Total interconnect delay = 2.659 ns ( 55.78 % )
Info: th for register "Y~reg0" (data pin = "S", clock pin = "CLK") is -3.818 ns
Info: + Longest clock path from clock "CLK" to destination register is 2.781 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'
Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y13_N2; Fanout = 1; REG Node = 'Y~reg0'
Info: Total cell delay = 2.180 ns ( 78.39 % )
Info: Total interconnect delay = 0.601 ns ( 21.61 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 6.614 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_109; Fanout = 1; PIN Node = 'S'
Info: 2: + IC(5.024 ns) + CELL(0.115 ns) = 6.614 ns; Loc. = LC_X26_Y13_N2; Fanout = 1; REG Node = 'Y~reg0'
Info: Total cell delay = 1.590 ns ( 24.04 % )
Info: Total interconnect delay = 5.024 ns ( 75.96 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Jun 21 18:27:38 2007
Info: Elapsed time: 00:00:01
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