📄 controll.tan.rpt
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Timing Analyzer report for controll
Thu Jun 21 18:27:38 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+---------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.311 ns ; K ; K1~reg0 ; -- ; CLK ; 0 ;
; Worst-case tco ; N/A ; None ; 7.758 ns ; K5~reg0 ; K5 ; CLK ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -3.818 ns ; S ; Y~reg0 ; -- ; CLK ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; K1~reg0 ; CLK ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------------------+---------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; K1~reg0 ; CLK ; CLK ; None ; None ; 3.264 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qe ; K4~reg0 ; CLK ; CLK ; None ; None ; 3.084 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; K4~reg0 ; K4~reg0 ; CLK ; CLK ; None ; None ; 2.826 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; K1~reg0 ; K1~reg0 ; CLK ; CLK ; None ; None ; 2.696 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; K4~reg0 ; CLK ; CLK ; None ; None ; 2.545 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; K6~reg0 ; CLK ; CLK ; None ; None ; 2.544 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; K5~reg0 ; CLK ; CLK ; None ; None ; 2.537 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; K2~reg0 ; K2~reg0 ; CLK ; CLK ; None ; None ; 2.428 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qf ; K2~reg0 ; CLK ; CLK ; None ; None ; 2.401 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; K3~reg0 ; CLK ; CLK ; None ; None ; 2.296 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qb ; K2~reg0 ; CLK ; CLK ; None ; None ; 2.291 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qf ; K1~reg0 ; CLK ; CLK ; None ; None ; 2.135 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qc ; K4~reg0 ; CLK ; CLK ; None ; None ; 2.033 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; K2~reg0 ; CLK ; CLK ; None ; None ; 2.029 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qb ; K1~reg0 ; CLK ; CLK ; None ; None ; 2.024 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qe ; K1~reg0 ; CLK ; CLK ; None ; None ; 1.992 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qc ; K1~reg0 ; CLK ; CLK ; None ; None ; 1.974 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qe ; K6~reg0 ; CLK ; CLK ; None ; None ; 1.959 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qc ; K2~reg0 ; CLK ; CLK ; None ; None ; 1.926 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qa ; K2~reg0 ; CLK ; CLK ; None ; None ; 1.918 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qa ; current_state.qb ; CLK ; CLK ; None ; None ; 1.897 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qd ; K1~reg0 ; CLK ; CLK ; None ; None ; 1.888 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; K3~reg0 ; K3~reg0 ; CLK ; CLK ; None ; None ; 1.848 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qf ; K6~reg0 ; CLK ; CLK ; None ; None ; 1.746 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qf ; K3~reg0 ; CLK ; CLK ; None ; None ; 1.732 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qd ; K2~reg0 ; CLK ; CLK ; None ; None ; 1.663 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qc ; current_state.qc ; CLK ; CLK ; None ; None ; 1.566 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qe ; K2~reg0 ; CLK ; CLK ; None ; None ; 1.473 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qf ; K5~reg0 ; CLK ; CLK ; None ; None ; 1.464 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qa ; K3~reg0 ; CLK ; CLK ; None ; None ; 1.404 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qe ; current_state.qf ; CLK ; CLK ; None ; None ; 1.400 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qe ; current_state.qe ; CLK ; CLK ; None ; None ; 1.393 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qf ; current_state.qg ; CLK ; CLK ; None ; None ; 1.189 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; current_state.qa ; CLK ; CLK ; None ; None ; 1.166 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qg ; current_state.qg ; CLK ; CLK ; None ; None ; 1.164 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qc ; current_state.qd ; CLK ; CLK ; None ; None ; 1.155 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qd ; current_state.qe ; CLK ; CLK ; None ; None ; 1.063 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qd ; current_state.qd ; CLK ; CLK ; None ; None ; 1.061 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; K6~reg0 ; K6~reg0 ; CLK ; CLK ; None ; None ; 1.045 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; K5~reg0 ; K5~reg0 ; CLK ; CLK ; None ; None ; 1.021 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qf ; current_state.qf ; CLK ; CLK ; None ; None ; 0.883 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qb ; current_state.qc ; CLK ; CLK ; None ; None ; 0.838 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.qb ; current_state.qb ; CLK ; CLK ; None ; None ; 0.837 ns ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+------------------+----------+
; N/A ; None ; 6.311 ns ; K ; K1~reg0 ; CLK ;
; N/A ; None ; 6.106 ns ; K ; K4~reg0 ; CLK ;
; N/A ; None ; 6.105 ns ; K ; K6~reg0 ; CLK ;
; N/A ; None ; 6.098 ns ; K ; K5~reg0 ; CLK ;
; N/A ; None ; 5.882 ns ; Qc2 ; K4~reg0 ; CLK ;
; N/A ; None ; 5.881 ns ; Qc2 ; K6~reg0 ; CLK ;
; N/A ; None ; 5.874 ns ; Qc2 ; K5~reg0 ; CLK ;
; N/A ; None ; 5.857 ns ; K ; K3~reg0 ; CLK ;
; N/A ; None ; 5.633 ns ; Qc2 ; K3~reg0 ; CLK ;
; N/A ; None ; 5.610 ns ; Qc2 ; K1~reg0 ; CLK ;
; N/A ; None ; 5.564 ns ; Qcl ; K2~reg0 ; CLK ;
; N/A ; None ; 5.297 ns ; Qcl ; K1~reg0 ; CLK ;
; N/A ; None ; 5.196 ns ; Qc2 ; K2~reg0 ; CLK ;
; N/A ; None ; 5.193 ns ; Qcl ; K6~reg0 ; CLK ;
; N/A ; None ; 4.993 ns ; K ; current_state.qf ; CLK ;
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