📄 controll.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register current_state.qg K1~reg0 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"current_state.qg\" and destination register \"K1~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.264 ns + Longest register register " "Info: + Longest register to register delay is 3.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.qg 1 REG LC_X3_Y10_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y10_N4; Fanout = 8; REG Node = 'current_state.qg'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { current_state.qg } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(0.292 ns) 1.431 ns K1~226 2 COMB LC_X1_Y10_N2 1 " "Info: 2: + IC(1.139 ns) + CELL(0.292 ns) = 1.431 ns; Loc. = LC_X1_Y10_N2; Fanout = 1; COMB Node = 'K1~226'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "1.431 ns" { current_state.qg K1~226 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.738 ns) 3.264 ns K1~reg0 3 REG LC_X2_Y10_N3 4 " "Info: 3: + IC(1.095 ns) + CELL(0.738 ns) = 3.264 ns; Loc. = LC_X2_Y10_N3; Fanout = 4; REG Node = 'K1~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "1.833 ns" { K1~226 K1~reg0 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.030 ns ( 31.56 % ) " "Info: Total cell delay = 1.030 ns ( 31.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.234 ns ( 68.44 % ) " "Info: Total interconnect delay = 2.234 ns ( 68.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "3.264 ns" { current_state.qg K1~226 K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.264 ns" { current_state.qg K1~226 K1~reg0 } { 0.000ns 1.139ns 1.095ns } { 0.000ns 0.292ns 0.738ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { CLK } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns K1~reg0 2 REG LC_X2_Y10_N3 4 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y10_N3; Fanout = 4; REG Node = 'K1~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "1.298 ns" { CLK K1~reg0 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 K1~reg0 } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.767 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { CLK } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns current_state.qg 2 REG LC_X3_Y10_N4 8 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X3_Y10_N4; Fanout = 8; REG Node = 'current_state.qg'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "1.298 ns" { CLK current_state.qg } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK current_state.qg } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 current_state.qg } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 K1~reg0 } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK current_state.qg } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 current_state.qg } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "3.264 ns" { current_state.qg K1~226 K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.264 ns" { current_state.qg K1~226 K1~reg0 } { 0.000ns 1.139ns 1.095ns } { 0.000ns 0.292ns 0.738ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 K1~reg0 } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK current_state.qg } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 current_state.qg } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { K1~reg0 } { } { } } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "K1~reg0 K CLK 6.311 ns register " "Info: tsu for register \"K1~reg0\" (data pin = \"K\", clock pin = \"CLK\") is 6.311 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.041 ns + Longest pin register " "Info: + Longest pin to register delay is 9.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns K 1 PIN PIN_11 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 10; PIN Node = 'K'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { K } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.149 ns) + CELL(0.590 ns) 7.208 ns K1~226 2 COMB LC_X1_Y10_N2 1 " "Info: 2: + IC(5.149 ns) + CELL(0.590 ns) = 7.208 ns; Loc. = LC_X1_Y10_N2; Fanout = 1; COMB Node = 'K1~226'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "5.739 ns" { K K1~226 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.738 ns) 9.041 ns K1~reg0 3 REG LC_X2_Y10_N3 4 " "Info: 3: + IC(1.095 ns) + CELL(0.738 ns) = 9.041 ns; Loc. = LC_X2_Y10_N3; Fanout = 4; REG Node = 'K1~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "1.833 ns" { K1~226 K1~reg0 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.797 ns ( 30.94 % ) " "Info: Total cell delay = 2.797 ns ( 30.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.244 ns ( 69.06 % ) " "Info: Total interconnect delay = 6.244 ns ( 69.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "9.041 ns" { K K1~226 K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.041 ns" { K K~out0 K1~226 K1~reg0 } { 0.000ns 0.000ns 5.149ns 1.095ns } { 0.000ns 1.469ns 0.590ns 0.738ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.767 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { CLK } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns K1~reg0 2 REG LC_X2_Y10_N3 4 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X2_Y10_N3; Fanout = 4; REG Node = 'K1~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "1.298 ns" { CLK K1~reg0 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 K1~reg0 } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "9.041 ns" { K K1~226 K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.041 ns" { K K~out0 K1~226 K1~reg0 } { 0.000ns 0.000ns 5.149ns 1.095ns } { 0.000ns 1.469ns 0.590ns 0.738ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK K1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 K1~reg0 } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK K5 K5~reg0 7.758 ns register " "Info: tco from clock \"CLK\" to destination pin \"K5\" through register \"K5~reg0\" is 7.758 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.767 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { CLK } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.587 ns) + CELL(0.711 ns) 2.767 ns K5~reg0 2 REG LC_X3_Y10_N2 2 " "Info: 2: + IC(0.587 ns) + CELL(0.711 ns) = 2.767 ns; Loc. = LC_X3_Y10_N2; Fanout = 2; REG Node = 'K5~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "1.298 ns" { CLK K5~reg0 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.79 % ) " "Info: Total cell delay = 2.180 ns ( 78.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.587 ns ( 21.21 % ) " "Info: Total interconnect delay = 0.587 ns ( 21.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK K5~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 K5~reg0 } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.767 ns + Longest register pin " "Info: + Longest register to pin delay is 4.767 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns K5~reg0 1 REG LC_X3_Y10_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y10_N2; Fanout = 2; REG Node = 'K5~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { K5~reg0 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.659 ns) + CELL(2.108 ns) 4.767 ns K5 2 PIN PIN_39 0 " "Info: 2: + IC(2.659 ns) + CELL(2.108 ns) = 4.767 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'K5'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "4.767 ns" { K5~reg0 K5 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 44.22 % ) " "Info: Total cell delay = 2.108 ns ( 44.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.659 ns ( 55.78 % ) " "Info: Total interconnect delay = 2.659 ns ( 55.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "4.767 ns" { K5~reg0 K5 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.767 ns" { K5~reg0 K5 } { 0.000ns 2.659ns } { 0.000ns 2.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.767 ns" { CLK K5~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.767 ns" { CLK CLK~out0 K5~reg0 } { 0.000ns 0.000ns 0.587ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "4.767 ns" { K5~reg0 K5 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.767 ns" { K5~reg0 K5 } { 0.000ns 2.659ns } { 0.000ns 2.108ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "Y~reg0 S CLK -3.818 ns register " "Info: th for register \"Y~reg0\" (data pin = \"S\", clock pin = \"CLK\") is -3.818 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.781 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 14; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { CLK } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns Y~reg0 2 REG LC_X26_Y13_N2 1 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X26_Y13_N2; Fanout = 1; REG Node = 'Y~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "1.312 ns" { CLK Y~reg0 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.39 % ) " "Info: Total cell delay = 2.180 ns ( 78.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns ( 21.61 % ) " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.781 ns" { CLK Y~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 Y~reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.614 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns S 1 PIN PIN_109 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_109; Fanout = 1; PIN Node = 'S'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "" { S } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.024 ns) + CELL(0.115 ns) 6.614 ns Y~reg0 2 REG LC_X26_Y13_N2 1 " "Info: 2: + IC(5.024 ns) + CELL(0.115 ns) = 6.614 ns; Loc. = LC_X26_Y13_N2; Fanout = 1; REG Node = 'Y~reg0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "5.139 ns" { S Y~reg0 } "NODE_NAME" } "" } } { "controll.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/s/controll.vhd" 82 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns ( 24.04 % ) " "Info: Total cell delay = 1.590 ns ( 24.04 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.024 ns ( 75.96 % ) " "Info: Total interconnect delay = 5.024 ns ( 75.96 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "6.614 ns" { S Y~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.614 ns" { S S~out0 Y~reg0 } { 0.000ns 0.000ns 5.024ns } { 0.000ns 1.475ns 0.115ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "2.781 ns" { CLK Y~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.781 ns" { CLK CLK~out0 Y~reg0 } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controll" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/s/db/controll.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/s/" "" "6.614 ns" { S Y~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.614 ns" { S S~out0 Y~reg0 } { 0.000ns 0.000ns 5.024ns } { 0.000ns 1.475ns 0.115ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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