controll.hier_info

用VHDL语言描述十六路彩灯的设计其开发均在FPGA中

|controll
K => K1~5.OUTPUTSELECT
K => K2~2.OUTPUTSELECT
K => K3~2.OUTPUTSELECT
K => K4~3.OUTPUTSELECT
K => K5~2.OUTPUTSELECT
K => K6~3.OUTPUTSELECT
K => current_state~1.OUTPUTSELECT
K => current_state~2.OUTPUTSELECT
K => current_state~3.OUTPUTSELECT
K => current_state~4.OUTPUTSELECT
K => current_state~5.OUTPUTSELECT
K => current_state~6.OUTPUTSELECT
K => current_state~7.OUTPUTSELECT
S => Y~reg0.DATAIN
Qcl => Select~1.IN3
Qcl => Select~4.IN3
Qcl => Select~5.IN3
Qcl => Select~4.IN1
Qcl => Select~0.IN2
Qcl => K1~2.OUTPUTSELECT
Qcl => Select~3.IN1
Qcl => K3~0.OUTPUTSELECT
Qcl => K5~0.OUTPUTSELECT
Qcl => K6~1.OUTPUTSELECT
Qcl => K1~0.OUTPUTSELECT
Qcl => K2~0.OUTPUTSELECT
Qcl => K4~1.OUTPUTSELECT
Qcl => K6~0.OUTPUTSELECT
Qc2 => Select~2.IN3
Qc2 => Select~3.IN3
Qc2 => current_state~0.DATAB
Qc2 => Select~2.IN1
Qc2 => Select~5.IN1
Qc2 => K1~3.OUTPUTSELECT
Qc2 => Select~1.IN1
Qc2 => K3~1.OUTPUTSELECT
Qc2 => K4~2.OUTPUTSELECT
Qc2 => K5~1.OUTPUTSELECT
Qc2 => K6~2.OUTPUTSELECT
Qc2 => K1~1.OUTPUTSELECT
Qc2 => K2~1.OUTPUTSELECT
Qc2 => K4~0.OUTPUTSELECT
CLK => K1~reg0.CLK
CLK => K2~reg0.CLK
CLK => K3~reg0.CLK
CLK => K4~reg0.CLK
CLK => K5~reg0.CLK
CLK => K6~reg0.CLK
CLK => Y~reg0.CLK
CLK => current_state~8.IN1
Y <= Y~reg0.DB_MAX_OUTPUT_PORT_TYPE
K1 <= K1~reg0.DB_MAX_OUTPUT_PORT_TYPE
K2 <= K2~reg0.DB_MAX_OUTPUT_PORT_TYPE
K3 <= K3~reg0.DB_MAX_OUTPUT_PORT_TYPE
K4 <= K4~reg0.DB_MAX_OUTPUT_PORT_TYPE
K5 <= K5~reg0.DB_MAX_OUTPUT_PORT_TYPE
K6 <= K6~reg0.DB_MAX_OUTPUT_PORT_TYPE