dianti.tan.qmsg

用VHDL 语言描述度八层电梯

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dd_cc\[4\] register en_up 149.12 MHz 6.706 ns Internal " "Info: Clock \"clk\" has Internal fmax of 149.12 MHz between source register \"dd_cc\[4\]\" and destination register \"en_up\" (period= 6.706 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.445 ns + Longest register register " "Info: + Longest register to register delay is 6.445 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dd_cc\[4\] 1 REG LC_X10_Y6_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y6_N0; Fanout = 5; REG Node = 'dd_cc\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { dd_cc[4] } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.181 ns) + CELL(0.292 ns) 1.473 ns LessThan~594 2 COMB LC_X10_Y6_N4 6 " "Info: 2: + IC(1.181 ns) + CELL(0.292 ns) = 1.473 ns; Loc. = LC_X10_Y6_N4; Fanout = 6; COMB Node = 'LessThan~594'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.473 ns" { dd_cc[4] LessThan~594 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.292 ns) 2.900 ns LessThan~595 3 COMB LC_X9_Y6_N7 4 " "Info: 3: + IC(1.135 ns) + CELL(0.292 ns) = 2.900 ns; Loc. = LC_X9_Y6_N7; Fanout = 4; COMB Node = 'LessThan~595'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.427 ns" { LessThan~594 LessThan~595 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.292 ns) 4.427 ns en_up~1713 4 COMB LC_X10_Y7_N1 1 " "Info: 4: + IC(1.235 ns) + CELL(0.292 ns) = 4.427 ns; Loc. = LC_X10_Y7_N1; Fanout = 1; COMB Node = 'en_up~1713'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.527 ns" { LessThan~595 en_up~1713 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.478 ns) 6.445 ns en_up 5 REG LC_X9_Y6_N9 5 " "Info: 5: + IC(1.540 ns) + CELL(0.478 ns) = 6.445 ns; Loc. = LC_X9_Y6_N9; Fanout = 5; REG Node = 'en_up'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.018 ns" { en_up~1713 en_up } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.354 ns ( 21.01 % ) " "Info: Total cell delay = 1.354 ns ( 21.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.091 ns ( 78.99 % ) " "Info: Total interconnect delay = 5.091 ns ( 78.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "6.445 ns" { dd_cc[4] LessThan~594 LessThan~595 en_up~1713 en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.445 ns" { dd_cc[4] LessThan~594 LessThan~595 en_up~1713 en_up } { 0.000ns 1.181ns 1.135ns 1.235ns 1.540ns } { 0.000ns 0.292ns 0.292ns 0.292ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { clk } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns en_up 2 REG LC_X9_Y6_N9 5 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X9_Y6_N9; Fanout = 5; REG Node = 'en_up'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.269 ns" { clk en_up } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 en_up } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.738 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { clk } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns dd_cc\[4\] 2 REG LC_X10_Y6_N0 5 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X10_Y6_N0; Fanout = 5; REG Node = 'dd_cc\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.269 ns" { clk dd_cc[4] } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk dd_cc[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 dd_cc[4] } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 en_up } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk dd_cc[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 dd_cc[4] } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "6.445 ns" { dd_cc[4] LessThan~594 LessThan~595 en_up~1713 en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.445 ns" { dd_cc[4] LessThan~594 LessThan~595 en_up~1713 en_up } { 0.000ns 1.181ns 1.135ns 1.235ns 1.540ns } { 0.000ns 0.292ns 0.292ns 0.292ns 0.478ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 en_up } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk dd_cc[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 dd_cc[4] } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "en_up g4 clk 11.447 ns register " "Info: tsu for register \"en_up\" (data pin = \"g4\", clock pin = \"clk\") is 11.447 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.148 ns + Longest pin register " "Info: + Longest pin to register delay is 14.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns g4 1 PIN PIN_51 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_51; Fanout = 8; PIN Node = 'g4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { g4 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.645 ns) + CELL(0.590 ns) 7.710 ns en_up~1709 2 COMB LC_X12_Y4_N5 4 " "Info: 2: + IC(5.645 ns) + CELL(0.590 ns) = 7.710 ns; Loc. = LC_X12_Y4_N5; Fanout = 4; COMB Node = 'en_up~1709'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "6.235 ns" { g4 en_up~1709 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.292 ns) 9.609 ns en_up~1710 3 COMB LC_X8_Y6_N4 2 " "Info: 3: + IC(1.607 ns) + CELL(0.292 ns) = 9.609 ns; Loc. = LC_X8_Y6_N4; Fanout = 2; COMB Node = 'en_up~1710'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.899 ns" { en_up~1709 en_up~1710 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.550 ns) + CELL(0.114 ns) 11.273 ns en_up~1711 4 COMB LC_X10_Y7_N0 1 " "Info: 4: + IC(1.550 ns) + CELL(0.114 ns) = 11.273 ns; Loc. = LC_X10_Y7_N0; Fanout = 1; COMB Node = 'en_up~1711'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.664 ns" { en_up~1710 en_up~1711 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.442 ns) 12.130 ns en_up~1713 5 COMB LC_X10_Y7_N1 1 " "Info: 5: + IC(0.415 ns) + CELL(0.442 ns) = 12.130 ns; Loc. = LC_X10_Y7_N1; Fanout = 1; COMB Node = 'en_up~1713'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "0.857 ns" { en_up~1711 en_up~1713 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.478 ns) 14.148 ns en_up 6 REG LC_X9_Y6_N9 5 " "Info: 6: + IC(1.540 ns) + CELL(0.478 ns) = 14.148 ns; Loc. = LC_X9_Y6_N9; Fanout = 5; REG Node = 'en_up'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.018 ns" { en_up~1713 en_up } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.391 ns ( 23.97 % ) " "Info: Total cell delay = 3.391 ns ( 23.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.757 ns ( 76.03 % ) " "Info: Total interconnect delay = 10.757 ns ( 76.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "14.148 ns" { g4 en_up~1709 en_up~1710 en_up~1711 en_up~1713 en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.148 ns" { g4 g4~out0 en_up~1709 en_up~1710 en_up~1711 en_up~1713 en_up } { 0.000ns 0.000ns 5.645ns 1.607ns 1.550ns 0.415ns 1.540ns } { 0.000ns 1.475ns 0.590ns 0.292ns 0.114ns 0.442ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.738 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { clk } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns en_up 2 REG LC_X9_Y6_N9 5 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X9_Y6_N9; Fanout = 5; REG Node = 'en_up'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.269 ns" { clk en_up } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 en_up } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "14.148 ns" { g4 en_up~1709 en_up~1710 en_up~1711 en_up~1713 en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.148 ns" { g4 g4~out0 en_up~1709 en_up~1710 en_up~1711 en_up~1713 en_up } { 0.000ns 0.000ns 5.645ns 1.607ns 1.550ns 0.415ns 1.540ns } { 0.000ns 1.475ns 0.590ns 0.292ns 0.114ns 0.442ns 0.478ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk en_up } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 en_up } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led_c_d\[4\] led_c_d\[4\]~reg0 8.064 ns register " "Info: tco from clock \"clk\" to destination pin \"led_c_d\[4\]\" through register \"led_c_d\[4\]~reg0\" is 8.064 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.738 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { clk } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns led_c_d\[4\]~reg0 2 REG LC_X11_Y7_N5 1 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X11_Y7_N5; Fanout = 1; REG Node = 'led_c_d\[4\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.269 ns" { clk led_c_d[4]~reg0 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk led_c_d[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 led_c_d[4]~reg0 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.102 ns + Longest register pin " "Info: + Longest register to pin delay is 5.102 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_c_d\[4\]~reg0 1 REG LC_X11_Y7_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y7_N5; Fanout = 1; REG Node = 'led_c_d\[4\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { led_c_d[4]~reg0 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.978 ns) + CELL(2.124 ns) 5.102 ns led_c_d\[4\] 2 PIN PIN_96 0 " "Info: 2: + IC(2.978 ns) + CELL(2.124 ns) = 5.102 ns; Loc. = PIN_96; Fanout = 0; PIN Node = 'led_c_d\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "5.102 ns" { led_c_d[4]~reg0 led_c_d[4] } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 41.63 % ) " "Info: Total cell delay = 2.124 ns ( 41.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.978 ns ( 58.37 % ) " "Info: Total interconnect delay = 2.978 ns ( 58.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "5.102 ns" { led_c_d[4]~reg0 led_c_d[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.102 ns" { led_c_d[4]~reg0 led_c_d[4] } { 0.000ns 2.978ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.738 ns" { clk led_c_d[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { clk clk~out0 led_c_d[4]~reg0 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "5.102 ns" { led_c_d[4]~reg0 led_c_d[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.102 ns" { led_c_d[4]~reg0 led_c_d[4] } { 0.000ns 2.978ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "d66 g6 clk -1.556 ns register " "Info: th for register \"d66\" (data pin = \"g6\", clock pin = \"clk\") is -1.556 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 79 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 79; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { clk } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns d66 2 REG LC_X10_Y4_N7 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X10_Y4_N7; Fanout = 4; REG Node = 'd66'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.261 ns" { clk d66 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.85 % ) " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns ( 20.15 % ) " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.730 ns" { clk d66 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 d66 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.301 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.301 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns g6 1 PIN PIN_16 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; PIN Node = 'g6'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "" { g6 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.376 ns) + CELL(0.442 ns) 3.287 ns rtl~1728 2 COMB LC_X10_Y4_N0 2 " "Info: 2: + IC(1.376 ns) + CELL(0.442 ns) = 3.287 ns; Loc. = LC_X10_Y4_N0; Fanout = 2; COMB Node = 'rtl~1728'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.818 ns" { g6 rtl~1728 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.607 ns) 4.301 ns d66 3 REG LC_X10_Y4_N7 4 " "Info: 3: + IC(0.407 ns) + CELL(0.607 ns) = 4.301 ns; Loc. = LC_X10_Y4_N7; Fanout = 4; REG Node = 'd66'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "1.014 ns" { rtl~1728 d66 } "NODE_NAME" } "" } } { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.518 ns ( 58.54 % ) " "Info: Total cell delay = 2.518 ns ( 58.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.783 ns ( 41.46 % ) " "Info: Total interconnect delay = 1.783 ns ( 41.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "4.301 ns" { g6 rtl~1728 d66 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.301 ns" { g6 g6~out0 rtl~1728 d66 } { 0.000ns 0.000ns 1.376ns 0.407ns } { 0.000ns 1.469ns 0.442ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "2.730 ns" { clk d66 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.730 ns" { clk clk~out0 d66 } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "dianti" "UNKNOWN" "V1" "F:/临时/EDA/电梯/db/dianti.quartus_db" { Floorplan "F:/临时/EDA/电梯/" "" "4.301 ns" { g6 rtl~1728 d66 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.301 ns" { g6 g6~out0 rtl~1728 d66 } { 0.000ns 0.000ns 1.376ns 0.407ns } { 0.000ns 1.469ns 0.442ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}