dianti.map.qmsg

用VHDL 语言描述度八层电梯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 20 17:49:33 2007 " "Info: Processing started: Wed Jun 20 17:49:33 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dianti -c dianti " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianti -c dianti" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianti.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dianti.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dianti-behav " "Info: Found design unit 1: dianti-behav" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dianti " "Info: Found entity 1: dianti" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dianti " "Info: Elaborating entity \"dianti\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "cc_u\[5\] data_in GND " "Warning: Reduced register \"cc_u\[5\]\" with stuck data_in port to stuck value GND" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "cc_d\[0\] data_in GND " "Warning: Reduced register \"cc_d\[0\]\" with stuck data_in port to stuck value GND" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led_c_u\[5\]~reg0 data_in GND " "Warning: Reduced register \"led_c_u\[5\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led_c_d\[0\]~reg0 data_in GND " "Warning: Reduced register \"led_c_d\[0\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "led\[3\]~reg0 led\[6\]~reg0 " "Info: Duplicate register \"led\[3\]~reg0\" merged to single register \"led\[6\]~reg0\"" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "led_c_u\[5\] GND " "Warning: Pin \"led_c_u\[5\]\" stuck at GND" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led_c_d\[0\] GND " "Warning: Pin \"led_c_d\[0\]\" stuck at GND" {  } { { "dianti.vhd" "" { Text "F:/临时/EDA/电梯/dianti.vhd" 35 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "236 " "Info: Implemented 236 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "27 " "Info: Implemented 27 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "177 " "Info: Implemented 177 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 20 17:49:41 2007 " "Info: Processing ended: Wed Jun 20 17:49:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}