ls.map.eqn

用VHDL 语言描述度三线八线译码器

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L5 is Mux~102
--operation mode is normal

A1L5 = !M[0] & !M[2] & !M[1];


--A1L6 is Mux~103
--operation mode is normal

A1L6 = M[0] & (!M[2] & !M[1]);


--A1L7 is Mux~104
--operation mode is normal

A1L7 = M[1] & (!M[0] & !M[2]);


--A1L8 is Mux~105
--operation mode is normal

A1L8 = M[0] & M[1] & (!M[2]);


--A1L9 is Mux~106
--operation mode is normal

A1L9 = M[2] & (!M[0] & !M[1]);


--A1L10 is Mux~107
--operation mode is normal

A1L10 = M[0] & M[2] & (!M[1]);


--A1L11 is Mux~108
--operation mode is normal

A1L11 = M[2] & M[1] & (!M[0]);


--A1L12 is Mux~109
--operation mode is normal

A1L12 = M[0] & M[2] & M[1];


--M[0] is M[0]
--operation mode is input

M[0] = INPUT();


--M[2] is M[2]
--operation mode is input

M[2] = INPUT();


--M[1] is M[1]
--operation mode is input

M[1] = INPUT();


--Y[0] is Y[0]
--operation mode is output

Y[0] = OUTPUT(A1L5);


--Y[1] is Y[1]
--operation mode is output

Y[1] = OUTPUT(A1L6);


--Y[2] is Y[2]
--operation mode is output

Y[2] = OUTPUT(A1L7);


--Y[3] is Y[3]
--operation mode is output

Y[3] = OUTPUT(A1L8);


--Y[4] is Y[4]
--operation mode is output

Y[4] = OUTPUT(A1L9);


--Y[5] is Y[5]
--operation mode is output

Y[5] = OUTPUT(A1L10);


--Y[6] is Y[6]
--operation mode is output

Y[6] = OUTPUT(A1L11);


--Y[7] is Y[7]
--operation mode is output

Y[7] = OUTPUT(A1L12);