ls.vhd

用VHDL 语言描述度三线八线译码器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LS IS
 PORT (M:IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
       Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY LS;
ARCHITECTURE ONE OF LS IS
BEGIN
PROCESS(M)
 BEGIN 
   CASE M IS
     WHEN "000"=>Y<="00000001";
     WHEN "001"=>Y<="00000010";
     WHEN "010"=>Y<="00000100";
     WHEN "011"=>Y<="00001000";
     WHEN "100"=>Y<="00010000";
     WHEN "101"=>Y<="00100000";
     WHEN "110"=>Y<="01000000";
     WHEN "111"=>Y<="10000000";
     WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
END ARCHITECTURE ONE;