decl7s.tan.qmsg

用VHDL 语言描述度7段LED数码显示管

{ "Info" "ITDB_TSU_RESULT" "LED7S\[4\]\$latch A\[0\] A\[2\] 2.333 ns register " "Info: tsu for register \"LED7S\[4\]\$latch\" (data pin = \"A\[0\]\", clock pin = \"A\[2\]\") is 2.333 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.688 ns + Longest pin register " "Info: + Longest pin to register delay is 9.688 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns A\[0\] 1 CLK PIN_140 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 8; CLK Node = 'A\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "" { A[0] } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.800 ns) + CELL(0.292 ns) 7.567 ns Mux~72 2 COMB LC_X6_Y4_N1 1 " "Info: 2: + IC(5.800 ns) + CELL(0.292 ns) = 7.567 ns; Loc. = LC_X6_Y4_N1; Fanout = 1; COMB Node = 'Mux~72'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "6.092 ns" { A[0] Mux~72 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.531 ns) + CELL(0.590 ns) 9.688 ns LED7S\[4\]\$latch 3 REG LC_X10_Y1_N2 1 " "Info: 3: + IC(1.531 ns) + CELL(0.590 ns) = 9.688 ns; Loc. = LC_X10_Y1_N2; Fanout = 1; REG Node = 'LED7S\[4\]\$latch'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "2.121 ns" { Mux~72 LED7S[4]$latch } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.357 ns ( 24.33 % ) " "Info: Total cell delay = 2.357 ns ( 24.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.331 ns ( 75.67 % ) " "Info: Total interconnect delay = 7.331 ns ( 75.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "9.688 ns" { A[0] Mux~72 LED7S[4]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.688 ns" { A[0] A[0]~out0 Mux~72 LED7S[4]$latch } { 0.000ns 0.000ns 5.800ns 1.531ns } { 0.000ns 1.475ns 0.292ns 0.590ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.842 ns + " "Info: + Micro setup delay of destination is 0.842 ns" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "A\[2\] destination 8.197 ns - Shortest register " "Info: - Shortest clock path from clock \"A\[2\]\" to destination register is 8.197 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns A\[2\] 1 CLK PIN_27 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 8; CLK Node = 'A\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "" { A[2] } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.538 ns) + CELL(0.292 ns) 3.299 ns Mux~68 2 COMB LC_X6_Y4_N6 7 " "Info: 2: + IC(1.538 ns) + CELL(0.292 ns) = 3.299 ns; Loc. = LC_X6_Y4_N6; Fanout = 7; COMB Node = 'Mux~68'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "1.830 ns" { A[2] Mux~68 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.784 ns) + CELL(0.114 ns) 8.197 ns LED7S\[4\]\$latch 3 REG LC_X10_Y1_N2 1 " "Info: 3: + IC(4.784 ns) + CELL(0.114 ns) = 8.197 ns; Loc. = LC_X10_Y1_N2; Fanout = 1; REG Node = 'LED7S\[4\]\$latch'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "4.898 ns" { Mux~68 LED7S[4]$latch } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.875 ns ( 22.87 % ) " "Info: Total cell delay = 1.875 ns ( 22.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.322 ns ( 77.13 % ) " "Info: Total interconnect delay = 6.322 ns ( 77.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "8.197 ns" { A[2] Mux~68 LED7S[4]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.197 ns" { A[2] A[2]~out0 Mux~68 LED7S[4]$latch } { 0.000ns 0.000ns 1.538ns 4.784ns } { 0.000ns 1.469ns 0.292ns 0.114ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "9.688 ns" { A[0] Mux~72 LED7S[4]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.688 ns" { A[0] A[0]~out0 Mux~72 LED7S[4]$latch } { 0.000ns 0.000ns 5.800ns 1.531ns } { 0.000ns 1.475ns 0.292ns 0.590ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "8.197 ns" { A[2] Mux~68 LED7S[4]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.197 ns" { A[2] A[2]~out0 Mux~68 LED7S[4]$latch } { 0.000ns 0.000ns 1.538ns 4.784ns } { 0.000ns 1.469ns 0.292ns 0.114ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "A\[0\] LED7S\[0\] LED7S\[0\]\$latch 12.647 ns register " "Info: tco from clock \"A\[0\]\" to destination pin \"LED7S\[0\]\" through register \"LED7S\[0\]\$latch\" is 12.647 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "A\[0\] source 8.654 ns + Longest register " "Info: + Longest clock path from clock \"A\[0\]\" to source register is 8.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns A\[0\] 1 CLK PIN_140 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 8; CLK Node = 'A\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "" { A[0] } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.866 ns) + CELL(0.114 ns) 3.455 ns Mux~68 2 COMB LC_X6_Y4_N6 7 " "Info: 2: + IC(1.866 ns) + CELL(0.114 ns) = 3.455 ns; Loc. = LC_X6_Y4_N6; Fanout = 7; COMB Node = 'Mux~68'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "1.980 ns" { A[0] Mux~68 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.907 ns) + CELL(0.292 ns) 8.654 ns LED7S\[0\]\$latch 3 REG LC_X6_Y4_N3 1 " "Info: 3: + IC(4.907 ns) + CELL(0.292 ns) = 8.654 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; REG Node = 'LED7S\[0\]\$latch'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "5.199 ns" { Mux~68 LED7S[0]$latch } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.881 ns ( 21.74 % ) " "Info: Total cell delay = 1.881 ns ( 21.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.773 ns ( 78.26 % ) " "Info: Total interconnect delay = 6.773 ns ( 78.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "8.654 ns" { A[0] Mux~68 LED7S[0]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.654 ns" { A[0] A[0]~out0 Mux~68 LED7S[0]$latch } { 0.000ns 0.000ns 1.866ns 4.907ns } { 0.000ns 1.475ns 0.114ns 0.292ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.993 ns + Longest register pin " "Info: + Longest register to pin delay is 3.993 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED7S\[0\]\$latch 1 REG LC_X6_Y4_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; REG Node = 'LED7S\[0\]\$latch'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "" { LED7S[0]$latch } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.885 ns) + CELL(2.108 ns) 3.993 ns LED7S\[0\] 2 PIN PIN_139 0 " "Info: 2: + IC(1.885 ns) + CELL(2.108 ns) = 3.993 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'LED7S\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "3.993 ns" { LED7S[0]$latch LED7S[0] } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 52.79 % ) " "Info: Total cell delay = 2.108 ns ( 52.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.885 ns ( 47.21 % ) " "Info: Total interconnect delay = 1.885 ns ( 47.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "3.993 ns" { LED7S[0]$latch LED7S[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.993 ns" { LED7S[0]$latch LED7S[0] } { 0.000ns 1.885ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "8.654 ns" { A[0] Mux~68 LED7S[0]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.654 ns" { A[0] A[0]~out0 Mux~68 LED7S[0]$latch } { 0.000ns 0.000ns 1.866ns 4.907ns } { 0.000ns 1.475ns 0.114ns 0.292ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "3.993 ns" { LED7S[0]$latch LED7S[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.993 ns" { LED7S[0]$latch LED7S[0] } { 0.000ns 1.885ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "LED7S\[0\]\$latch A\[1\] A\[0\] 0.838 ns register " "Info: th for register \"LED7S\[0\]\$latch\" (data pin = \"A\[1\]\", clock pin = \"A\[0\]\") is 0.838 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "A\[0\] destination 8.654 ns + Longest register " "Info: + Longest clock path from clock \"A\[0\]\" to destination register is 8.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns A\[0\] 1 CLK PIN_140 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 8; CLK Node = 'A\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "" { A[0] } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.866 ns) + CELL(0.114 ns) 3.455 ns Mux~68 2 COMB LC_X6_Y4_N6 7 " "Info: 2: + IC(1.866 ns) + CELL(0.114 ns) = 3.455 ns; Loc. = LC_X6_Y4_N6; Fanout = 7; COMB Node = 'Mux~68'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "1.980 ns" { A[0] Mux~68 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.907 ns) + CELL(0.292 ns) 8.654 ns LED7S\[0\]\$latch 3 REG LC_X6_Y4_N3 1 " "Info: 3: + IC(4.907 ns) + CELL(0.292 ns) = 8.654 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; REG Node = 'LED7S\[0\]\$latch'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "5.199 ns" { Mux~68 LED7S[0]$latch } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.881 ns ( 21.74 % ) " "Info: Total cell delay = 1.881 ns ( 21.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.773 ns ( 78.26 % ) " "Info: Total interconnect delay = 6.773 ns ( 78.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "8.654 ns" { A[0] Mux~68 LED7S[0]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.654 ns" { A[0] A[0]~out0 Mux~68 LED7S[0]$latch } { 0.000ns 0.000ns 1.866ns 4.907ns } { 0.000ns 1.475ns 0.114ns 0.292ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.816 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns A\[1\] 1 CLK PIN_42 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_42; Fanout = 8; CLK Node = 'A\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "" { A[1] } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.208 ns) + CELL(0.114 ns) 6.797 ns Mux~67 2 COMB LC_X6_Y4_N2 1 " "Info: 2: + IC(5.208 ns) + CELL(0.114 ns) = 6.797 ns; Loc. = LC_X6_Y4_N2; Fanout = 1; COMB Node = 'Mux~67'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "5.322 ns" { A[1] Mux~67 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.429 ns) + CELL(0.590 ns) 7.816 ns LED7S\[0\]\$latch 3 REG LC_X6_Y4_N3 1 " "Info: 3: + IC(0.429 ns) + CELL(0.590 ns) = 7.816 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; REG Node = 'LED7S\[0\]\$latch'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "1.019 ns" { Mux~67 LED7S[0]$latch } "NODE_NAME" } "" } } { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.179 ns ( 27.88 % ) " "Info: Total cell delay = 2.179 ns ( 27.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.637 ns ( 72.12 % ) " "Info: Total interconnect delay = 5.637 ns ( 72.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "7.816 ns" { A[1] Mux~67 LED7S[0]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.816 ns" { A[1] A[1]~out0 Mux~67 LED7S[0]$latch } { 0.000ns 0.000ns 5.208ns 0.429ns } { 0.000ns 1.475ns 0.114ns 0.590ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "8.654 ns" { A[0] Mux~68 LED7S[0]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.654 ns" { A[0] A[0]~out0 Mux~68 LED7S[0]$latch } { 0.000ns 0.000ns 1.866ns 4.907ns } { 0.000ns 1.475ns 0.114ns 0.292ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DECL7S" "UNKNOWN" "V1" "F:/临时/EDA/7段LED/db/DECL7S.quartus_db" { Floorplan "F:/临时/EDA/7段LED/" "" "7.816 ns" { A[1] Mux~67 LED7S[0]$latch } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.816 ns" { A[1] A[1]~out0 Mux~67 LED7S[0]$latch } { 0.000ns 0.000ns 5.208ns 0.429ns } { 0.000ns 1.475ns 0.114ns 0.590ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 18 00:24:23 2007 " "Info: Processing ended: Mon Jun 18 00:24:23 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}