decl7s.tan.qmsg

用VHDL 语言描述度7段LED数码显示管

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 18 00:24:22 2007 " "Info: Processing started: Mon Jun 18 00:24:22 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DECL7S -c DECL7S --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DECL7S -c DECL7S --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "LED7S\[0\]\$latch " "Warning: Node \"LED7S\[0\]\$latch\" is a latch" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED7S\[1\]\$latch " "Warning: Node \"LED7S\[1\]\$latch\" is a latch" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED7S\[2\]\$latch " "Warning: Node \"LED7S\[2\]\$latch\" is a latch" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED7S\[3\]\$latch " "Warning: Node \"LED7S\[3\]\$latch\" is a latch" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED7S\[4\]\$latch " "Warning: Node \"LED7S\[4\]\$latch\" is a latch" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED7S\[5\]\$latch " "Warning: Node \"LED7S\[5\]\$latch\" is a latch" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "LED7S\[6\]\$latch " "Warning: Node \"LED7S\[6\]\$latch\" is a latch" {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "A\[1\] " "Info: Assuming node \"A\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "A\[3\] " "Info: Assuming node \"A\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "A\[2\] " "Info: Assuming node \"A\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "A\[0\] " "Info: Assuming node \"A\[0\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "DECL7S.vhd" "" { Text "F:/临时/EDA/7段LED/DECL7S.vhd" 4 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux~68 " "Info: Detected gated clock \"Mux~68\" as buffer" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Mux~68" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}