decl7s.map.rpt

用VHDL 语言描述度7段LED数码显示管

+----------------------------------+-----------------+-----------------+-------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 15    ;
;     -- Combinational with no register       ; 15    ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 8     ;
;     -- 3 input functions                    ; 7     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 15    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 11    ;
; Maximum fan-out node                        ; A[0]  ;
; Maximum fan-out                             ; 8     ;
; Total fan-out                               ; 60    ;
; Average fan-out                             ; 2.31  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |DECL7S                    ; 15 (15)     ; 0            ; 0           ; 11   ; 0            ; 15 (15)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |DECL7S             ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; LED7S[0]$latch                                ;   ;
; LED7S[1]$latch                                ;   ;
; LED7S[2]$latch                                ;   ;
; LED7S[3]$latch                                ;   ;
; LED7S[4]$latch                                ;   ;
; LED7S[5]$latch                                ;   ;
; LED7S[6]$latch                                ;   ;
; Number of user-specified and inferred latches ; 7 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/临时/EDA/7段LED/DECL7S.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Jun 18 00:24:05 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DECL7S -c DECL7S
Info: Found 2 design units, including 1 entities, in source file DECL7S.vhd
    Info: Found design unit 1: DECL7S-one
    Info: Found entity 1: DECL7S
Info: Elaborating entity "DECL7S" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at DECL7S.vhd(9): signal or variable "LED7S" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "LED7S" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Latch LED7S[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal A[0]
Warning: Latch LED7S[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal A[0]
Warning: Latch LED7S[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal A[0]
Warning: Latch LED7S[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal A[0]
Warning: Latch LED7S[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal A[0]
Warning: Latch LED7S[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal A[0]
Warning: Latch LED7S[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal A[0]
Info: Implemented 26 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 7 output pins
    Info: Implemented 15 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
    Info: Processing ended: Mon Jun 18 00:24:09 2007
    Info: Elapsed time: 00:00:04