decl7s.tan.rpt

用VHDL 语言描述度7段LED数码显示管

; N/A           ; None        ; -0.555 ns ; A[1] ; LED7S[6]$latch ; A[2]     ;
; N/A           ; None        ; -0.556 ns ; A[1] ; LED7S[1]$latch ; A[2]     ;
; N/A           ; None        ; -0.564 ns ; A[1] ; LED7S[3]$latch ; A[0]     ;
; N/A           ; None        ; -0.567 ns ; A[1] ; LED7S[4]$latch ; A[0]     ;
; N/A           ; None        ; -0.614 ns ; A[1] ; LED7S[3]$latch ; A[3]     ;
; N/A           ; None        ; -0.617 ns ; A[1] ; LED7S[4]$latch ; A[3]     ;
; N/A           ; None        ; -0.652 ns ; A[1] ; LED7S[3]$latch ; A[1]     ;
; N/A           ; None        ; -0.655 ns ; A[1] ; LED7S[4]$latch ; A[1]     ;
; N/A           ; None        ; -0.720 ns ; A[1] ; LED7S[3]$latch ; A[2]     ;
; N/A           ; None        ; -0.723 ns ; A[1] ; LED7S[4]$latch ; A[2]     ;
; N/A           ; None        ; -0.903 ns ; A[2] ; LED7S[5]$latch ; A[0]     ;
; N/A           ; None        ; -0.920 ns ; A[2] ; LED7S[6]$latch ; A[0]     ;
; N/A           ; None        ; -0.921 ns ; A[2] ; LED7S[1]$latch ; A[0]     ;
; N/A           ; None        ; -0.953 ns ; A[2] ; LED7S[5]$latch ; A[3]     ;
; N/A           ; None        ; -0.970 ns ; A[2] ; LED7S[6]$latch ; A[3]     ;
; N/A           ; None        ; -0.971 ns ; A[2] ; LED7S[1]$latch ; A[3]     ;
; N/A           ; None        ; -0.991 ns ; A[2] ; LED7S[5]$latch ; A[1]     ;
; N/A           ; None        ; -1.008 ns ; A[2] ; LED7S[6]$latch ; A[1]     ;
; N/A           ; None        ; -1.009 ns ; A[2] ; LED7S[1]$latch ; A[1]     ;
; N/A           ; None        ; -1.059 ns ; A[2] ; LED7S[5]$latch ; A[2]     ;
; N/A           ; None        ; -1.076 ns ; A[2] ; LED7S[6]$latch ; A[2]     ;
; N/A           ; None        ; -1.077 ns ; A[2] ; LED7S[1]$latch ; A[2]     ;
; N/A           ; None        ; -1.085 ns ; A[2] ; LED7S[3]$latch ; A[0]     ;
; N/A           ; None        ; -1.090 ns ; A[3] ; LED7S[5]$latch ; A[0]     ;
; N/A           ; None        ; -1.097 ns ; A[2] ; LED7S[4]$latch ; A[0]     ;
; N/A           ; None        ; -1.098 ns ; A[3] ; LED7S[6]$latch ; A[0]     ;
; N/A           ; None        ; -1.100 ns ; A[3] ; LED7S[1]$latch ; A[0]     ;
; N/A           ; None        ; -1.135 ns ; A[2] ; LED7S[3]$latch ; A[3]     ;
; N/A           ; None        ; -1.140 ns ; A[3] ; LED7S[5]$latch ; A[3]     ;
; N/A           ; None        ; -1.147 ns ; A[2] ; LED7S[4]$latch ; A[3]     ;
; N/A           ; None        ; -1.148 ns ; A[3] ; LED7S[6]$latch ; A[3]     ;
; N/A           ; None        ; -1.150 ns ; A[3] ; LED7S[1]$latch ; A[3]     ;
; N/A           ; None        ; -1.168 ns ; A[0] ; LED7S[5]$latch ; A[0]     ;
; N/A           ; None        ; -1.168 ns ; A[0] ; LED7S[6]$latch ; A[0]     ;
; N/A           ; None        ; -1.169 ns ; A[0] ; LED7S[1]$latch ; A[0]     ;
; N/A           ; None        ; -1.173 ns ; A[2] ; LED7S[3]$latch ; A[1]     ;
; N/A           ; None        ; -1.178 ns ; A[3] ; LED7S[5]$latch ; A[1]     ;
; N/A           ; None        ; -1.185 ns ; A[2] ; LED7S[4]$latch ; A[1]     ;
; N/A           ; None        ; -1.186 ns ; A[3] ; LED7S[6]$latch ; A[1]     ;
; N/A           ; None        ; -1.188 ns ; A[3] ; LED7S[1]$latch ; A[1]     ;
; N/A           ; None        ; -1.218 ns ; A[0] ; LED7S[5]$latch ; A[3]     ;
; N/A           ; None        ; -1.218 ns ; A[0] ; LED7S[6]$latch ; A[3]     ;
; N/A           ; None        ; -1.219 ns ; A[0] ; LED7S[1]$latch ; A[3]     ;
; N/A           ; None        ; -1.241 ns ; A[2] ; LED7S[3]$latch ; A[2]     ;
; N/A           ; None        ; -1.246 ns ; A[3] ; LED7S[5]$latch ; A[2]     ;
; N/A           ; None        ; -1.253 ns ; A[2] ; LED7S[4]$latch ; A[2]     ;
; N/A           ; None        ; -1.254 ns ; A[3] ; LED7S[6]$latch ; A[2]     ;
; N/A           ; None        ; -1.256 ns ; A[0] ; LED7S[5]$latch ; A[1]     ;
; N/A           ; None        ; -1.256 ns ; A[0] ; LED7S[6]$latch ; A[1]     ;
; N/A           ; None        ; -1.256 ns ; A[3] ; LED7S[1]$latch ; A[2]     ;
; N/A           ; None        ; -1.257 ns ; A[0] ; LED7S[1]$latch ; A[1]     ;
; N/A           ; None        ; -1.264 ns ; A[3] ; LED7S[3]$latch ; A[0]     ;
; N/A           ; None        ; -1.272 ns ; A[3] ; LED7S[4]$latch ; A[0]     ;
; N/A           ; None        ; -1.314 ns ; A[3] ; LED7S[3]$latch ; A[3]     ;
; N/A           ; None        ; -1.322 ns ; A[3] ; LED7S[4]$latch ; A[3]     ;
; N/A           ; None        ; -1.324 ns ; A[0] ; LED7S[5]$latch ; A[2]     ;
; N/A           ; None        ; -1.324 ns ; A[0] ; LED7S[6]$latch ; A[2]     ;
; N/A           ; None        ; -1.325 ns ; A[0] ; LED7S[1]$latch ; A[2]     ;
; N/A           ; None        ; -1.332 ns ; A[0] ; LED7S[3]$latch ; A[0]     ;
; N/A           ; None        ; -1.335 ns ; A[0] ; LED7S[4]$latch ; A[0]     ;
; N/A           ; None        ; -1.352 ns ; A[3] ; LED7S[3]$latch ; A[1]     ;
; N/A           ; None        ; -1.360 ns ; A[3] ; LED7S[4]$latch ; A[1]     ;
; N/A           ; None        ; -1.382 ns ; A[0] ; LED7S[3]$latch ; A[3]     ;
; N/A           ; None        ; -1.385 ns ; A[0] ; LED7S[4]$latch ; A[3]     ;
; N/A           ; None        ; -1.420 ns ; A[0] ; LED7S[3]$latch ; A[1]     ;
; N/A           ; None        ; -1.420 ns ; A[3] ; LED7S[3]$latch ; A[2]     ;
; N/A           ; None        ; -1.423 ns ; A[0] ; LED7S[4]$latch ; A[1]     ;
; N/A           ; None        ; -1.428 ns ; A[3] ; LED7S[4]$latch ; A[2]     ;
; N/A           ; None        ; -1.488 ns ; A[0] ; LED7S[3]$latch ; A[2]     ;
; N/A           ; None        ; -1.491 ns ; A[0] ; LED7S[4]$latch ; A[2]     ;
+---------------+-------------+-----------+------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Jun 18 00:24:22 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DECL7S -c DECL7S --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "LED7S[0]$latch" is a latch
    Warning: Node "LED7S[1]$latch" is a latch
    Warning: Node "LED7S[2]$latch" is a latch
    Warning: Node "LED7S[3]$latch" is a latch
    Warning: Node "LED7S[4]$latch" is a latch
    Warning: Node "LED7S[5]$latch" is a latch
    Warning: Node "LED7S[6]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "A[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "A[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "A[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "A[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Mux~68" as buffer
Info: tsu for register "LED7S[4]$latch" (data pin = "A[0]", clock pin = "A[2]") is 2.333 ns
    Info: + Longest pin to register delay is 9.688 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 8; CLK Node = 'A[0]'
        Info: 2: + IC(5.800 ns) + CELL(0.292 ns) = 7.567 ns; Loc. = LC_X6_Y4_N1; Fanout = 1; COMB Node = 'Mux~72'
        Info: 3: + IC(1.531 ns) + CELL(0.590 ns) = 9.688 ns; Loc. = LC_X10_Y1_N2; Fanout = 1; REG Node = 'LED7S[4]$latch'
        Info: Total cell delay = 2.357 ns ( 24.33 % )
        Info: Total interconnect delay = 7.331 ns ( 75.67 % )
    Info: + Micro setup delay of destination is 0.842 ns
    Info: - Shortest clock path from clock "A[2]" to destination register is 8.197 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 8; CLK Node = 'A[2]'
        Info: 2: + IC(1.538 ns) + CELL(0.292 ns) = 3.299 ns; Loc. = LC_X6_Y4_N6; Fanout = 7; COMB Node = 'Mux~68'
        Info: 3: + IC(4.784 ns) + CELL(0.114 ns) = 8.197 ns; Loc. = LC_X10_Y1_N2; Fanout = 1; REG Node = 'LED7S[4]$latch'
        Info: Total cell delay = 1.875 ns ( 22.87 % )
        Info: Total interconnect delay = 6.322 ns ( 77.13 % )
Info: tco from clock "A[0]" to destination pin "LED7S[0]" through register "LED7S[0]$latch" is 12.647 ns
    Info: + Longest clock path from clock "A[0]" to source register is 8.654 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 8; CLK Node = 'A[0]'
        Info: 2: + IC(1.866 ns) + CELL(0.114 ns) = 3.455 ns; Loc. = LC_X6_Y4_N6; Fanout = 7; COMB Node = 'Mux~68'
        Info: 3: + IC(4.907 ns) + CELL(0.292 ns) = 8.654 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; REG Node = 'LED7S[0]$latch'
        Info: Total cell delay = 1.881 ns ( 21.74 % )
        Info: Total interconnect delay = 6.773 ns ( 78.26 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 3.993 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; REG Node = 'LED7S[0]$latch'
        Info: 2: + IC(1.885 ns) + CELL(2.108 ns) = 3.993 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'LED7S[0]'
        Info: Total cell delay = 2.108 ns ( 52.79 % )
        Info: Total interconnect delay = 1.885 ns ( 47.21 % )
Info: th for register "LED7S[0]$latch" (data pin = "A[1]", clock pin = "A[0]") is 0.838 ns
    Info: + Longest clock path from clock "A[0]" to destination register is 8.654 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 8; CLK Node = 'A[0]'
        Info: 2: + IC(1.866 ns) + CELL(0.114 ns) = 3.455 ns; Loc. = LC_X6_Y4_N6; Fanout = 7; COMB Node = 'Mux~68'
        Info: 3: + IC(4.907 ns) + CELL(0.292 ns) = 8.654 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; REG Node = 'LED7S[0]$latch'
        Info: Total cell delay = 1.881 ns ( 21.74 % )
        Info: Total interconnect delay = 6.773 ns ( 78.26 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 7.816 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_42; Fanout = 8; CLK Node = 'A[1]'
        Info: 2: + IC(5.208 ns) + CELL(0.114 ns) = 6.797 ns; Loc. = LC_X6_Y4_N2; Fanout = 1; COMB Node = 'Mux~67'
        Info: 3: + IC(0.429 ns) + CELL(0.590 ns) = 7.816 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; REG Node = 'LED7S[0]$latch'
        Info: Total cell delay = 2.179 ns ( 27.88 % )
        Info: Total interconnect delay = 5.637 ns ( 72.12 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings
    Info: Processing ended: Mon Jun 18 00:24:23 2007
    Info: Elapsed time: 00:00:01