📄 adv7123.c
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_IIC_write(hI2C, _ADV7123_IICADDR,0x6D,&charPtr[0x6D],1);
}
/*
* ======== setVideoDisplay ========
*/
static void setVideoDisplay(ADV7123_Mode displayType,
ADV7123_AnalogFormat outMode, ADV7123_InputFormat inFormat, Bool enableBT656Sync)
{
Uint8 *charPtr;
Uns activePixels,activeLines;
Uns hLen;
Uns hStart,hEnd,fal, lal;
volatile _ADV7123_Regs *regPtr = (_ADV7123_Regs *)&_ADV7123_settingsDef;
Uns yOffset;
Uns xOffset;
Uns yInc = 0;
Uns ySkip = 0;
Uns yIWGTO = 100;
Uns yIWGTE = 100;
Uns xInc = 0;
hStart = 272;
xOffset = modeTbl[displayType][0];
yOffset = modeTbl[displayType][1];
hLen = modeTbl[displayType][2];;
activePixels = modeTbl[displayType][3];
activeLines = modeTbl[displayType][4];
regPtr->inputFormat = modeTbl[displayType][5];
regPtr->pixClock0 = modeTbl[displayType][6];
regPtr->pixClock1 = modeTbl[displayType][7];
regPtr->pixClock2 = modeTbl[displayType][8];
regPtr->chromaBinary = 1;
regPtr->compSyncEnable = 0;
regPtr->encOff = 1;
regPtr->idel = 1;
fal = 18;
if(regPtr->inputFormat == ADV7123_IFMT_YCBCR422_NONEINTERLACED) {
/* 54MHz input clock (input mode 3) */
xInc = 0;
regPtr->edge = 0;
regPtr->slot = 1;
} else if(regPtr->inputFormat == ADV7123_IFMT_YCBCR422_INTERLACED){
/* 27MHz input clock (input mode 4) */
xInc = 2048;
regPtr->edge = 1;
regPtr->slot = 0;
regPtr->encOff = 0;
regPtr->idel = 3;
regPtr->compSyncEnable = 0;
} else if(regPtr->inputFormat == ADV7123_IFMT_RGB565) {
xInc = 0;
regPtr->edge = 1;
regPtr->slot = 1;
regPtr->chromaBinary = 0;
}
if(displayType == ADV7123_MODE_PAL720) {
regPtr->palEnable = 1;
regPtr->fise = 0;
regPtr->burstStart = 0x21;
regPtr->burstEnd = 0x1d;
regPtr->chromaPhase = 0x6b;
regPtr->burstAmplitude = 0x2d;
regPtr->subCarrier0 = 0xCB;
regPtr->subCarrier1 = 0x8A;
regPtr->subCarrier2 = 0x09;
regPtr->subCarrier3 = 0x2A;
regPtr->hTriggerMSBs = 0;
regPtr->hTrigger = 2;
if(enableBT656Sync) {
hStart = 280;
xOffset = 0;
regPtr->syncVia656 = 1;
fal = 21;
regPtr->vTrigger = 0;
}
else {
hStart = 284;
regPtr->syncVia656 = 0;
fal = 21;
regPtr->vTrigger = 2;
}
regPtr->lumaDelay = 0;
regPtr->cbGain = 0x7b;
regPtr->crGain = 0xAe;
} else if(displayType == ADV7123_MODE_NTSC720){
regPtr->hTriggerMSBs = 0;
regPtr->hTrigger = 2;
if(enableBT656Sync) {
regPtr->vTrigNegative = 1;
regPtr->vTrigger = 4;
fal = 13;
activeLines += 3;
xOffset = 0;
regPtr->syncVia656 = 1;
}
else {
regPtr->vTrigNegative = 0;
regPtr->vTrigger = 0;
fal = 17;
regPtr->syncVia656 = 0;
}
regPtr->lumaDelay = 0;
regPtr->chromaPhase = 0x33;
regPtr->burstAmplitude = 0x3F;
regPtr->subCarrier0 = 0x1F;
regPtr->subCarrier1 = 0x7C;
regPtr->subCarrier2 = 0xF0;
regPtr->subCarrier3 = 0x21;
regPtr->cbGain = 0x7b;
regPtr->crGain = 0xAe;
}
regPtr->hLen = hLen;
regPtr->hLenMsb = hLen >> 8;
regPtr->xInc = xInc;
regPtr->xIncMsb = xInc >> 8;
regPtr->yInc = yInc;
regPtr->yIncMsb = yInc >> 8;
regPtr->yIWGTO = yIWGTO;
regPtr->yIWGTOMsb = yIWGTO >> 8;
regPtr->yIWGTE = yIWGTE;
regPtr->yIWGTEMsb = yIWGTE >> 8;
regPtr->ySkip = ySkip;
regPtr->ySkipMsb = ySkip >> 8;
hEnd = hStart + (2 * activePixels);
regPtr->hStart = hStart;
regPtr->hEnd = hEnd;
regPtr->hStartMSB = hStart >> 8;
regPtr->hEndMSB = hEnd >> 8;
if(regPtr->inputFormat != ADV7123_IFMT_YCBCR422_INTERLACED){
activePixels /= 2;
}
regPtr->xPix = activePixels;
regPtr->xPixMsb = activePixels >> 8;
regPtr->yPix = activeLines;
regPtr->yPixMsb = activeLines >> 8;
lal = fal + activeLines;
regPtr->fal = fal;
regPtr->falMsb = fal >> 8;
regPtr->lal = lal;
regPtr->lalMsb = lal >> 8;
regPtr->xOfs = xOffset;
regPtr->xOfsMsb = xOffset >> 8;
regPtr->yOfsOdd = yOffset;
regPtr->yOfsOddMsb = yOffset >> 8;
regPtr->yOfsEven = yOffset;
regPtr->yOfsEvenMsb = yOffset >> 8;
charPtr = (Uint8 *)&_ADV7123_settingsDef;
_IIC_write(hI2C, _ADV7123_IICADDR,1,&charPtr[1],0xA3);
_IIC_write(hI2C, _ADV7123_IICADDR,0xfd,&charPtr[0xfd],1);
if(displayType >= ADV7123_MODE_VGA){
clearHDSyncEngine();
loadHDSyncEngine(displayType);
startHDSyncEngine(displayType);
setOutputMode(ADV7123_AFMT_RGB);
/* reset the OSD_FPGA and configure it in approciate mode */
*(volatile Uint8 *)(0x90080010) = 0x20; // 16-bit mode
}else{
setOutputMode(outMode);
/* reset the OSD_FPGA and configure it in approciate mode */
*(volatile Uint8 *)(0x90080010) = 0x28; // 8-bit mode
}
*(volatile Uint8 *)(0x90080010) &= ~0x20; // un-reset OSD FPGA */
while(!(*(volatile Uint8 *)(0x90080013) & 0x40));
}
/*
* ======== startHDSyncEngine ========
*/
static void startHDSyncEngine(ADV7123_Mode displayType)
{
_ADV7123_Regs *regPtr;
Uint8 *charPtr;
regPtr = &_ADV7123_settingsDef;
regPtr->hdRGB_YCbCr = 0;
regPtr->hdFullGain = 1;
regPtr->hdTriggerPhaseY = 0;
switch(displayType) {
case ADV7123_MODE_VGA:
regPtr->hdLineCounter = 2;
regPtr->hdTriggerPhaseX = 12;
break;
case ADV7123_MODE_SVGA:
regPtr->hdLineCounter = 4;
regPtr->hdTriggerPhaseX = 12;
break;
case ADV7123_MODE_XGA:
regPtr->hdLineCounter = 6;
regPtr->hdTriggerPhaseX = 12;
break;
case ADV7123_MODE_HD1080I30F:
regPtr->hdLineCounter = 2;
regPtr->hdTriggerPhaseX = 0;
regPtr->hdRGB_YCbCr = 1;
regPtr->hdFullGain = 0;
regPtr->hdTriggerPhaseY = 95;
break;
case ADV7123_MODE_HD480P60F:
regPtr->hdLineCounter = 2;
regPtr->hdTriggerPhaseX = 5;
regPtr->hdRGB_YCbCr = 1;
regPtr->hdFullGain = 0;
regPtr->hdTriggerPhaseY = 0;
break;
case ADV7123_MODE_HD720P60F:
regPtr->hdLineCounter = 2;
regPtr->hdTriggerPhaseX = 15;
regPtr->hdRGB_YCbCr = 1;
regPtr->hdFullGain = 0;
regPtr->hdTriggerPhaseY = 0;
break;
default:
regPtr->hdLineCounter = 2;
regPtr->hdTriggerPhaseX = 5;
regPtr->hdRGB_YCbCr = 1;
regPtr->hdFullGain = 0;
regPtr->hdTriggerPhaseY = 0;
break;
}
regPtr->hdLineTypePtr = 0;
regPtr->hdLinePatternPtr = 0;
regPtr->hdDurationCtr = 0;
regPtr->hdEventTypePtr = 0;
regPtr->hdColorInterpolator = 1;
regPtr->hdActive = 1;
charPtr = (Uint8 *)&_ADV7123_settingsDef;
_IIC_write(hI2C, _ADV7123_IICADDR,0xD4,&charPtr[0xD4],9);
return;
}
/*
* ======== ADV7123_close ========
*/
static Int ADV7123_close(EDC_Handle handle)
{
Int devId = (Int)handle;
/*First Check if the Handle is correct */
if(devId == _ADV7123_IICADDR) {
/*Put _ADV7123 in power down mode */
powerdownADV7123(TRUE);
return EDC_SUCCESS;
} else
return EDC_FAILED;
}
/*
* ======== ADV7123_ctrl ========
*/
static Int ADV7123_ctrl(EDC_Handle handle, ADV7123_Cmd cmd, Arg param)
{
Int devId = (Int)handle;
/*First Check if the Handle is correct */
if(devId != _ADV7123_IICADDR){
return EDC_FAILED;
}
switch(cmd) {
case EDC_CONFIG: {
ADV7123_ConfParams *ADV7123Params = (ADV7123_ConfParams *)param;
hI2C = ADV7123Params->hI2C;
configADV7123(ADV7123Params->mode, ADV7123Params->enableSlaveMode,
ADV7123Params->aFmt, ADV7123Params->iFmt, ADV7123Params->enableBT656Sync);
setADV7123SyncMode(ADV7123Params->mode,
ADV7123Params->enableBT656Sync);
}
break;
case EDC_RESET:
resetADV7123();
break;
case ADV7123_POWERDOWN:
powerdownADV7123(TRUE);
break;
case ADV7123_POWERUP:
powerdownADV7123(FALSE);
break;
case ADV7123_ENABLE_SLAVE_MODE:
enableSlaveMode((Bool)param);
break;
case ADV7123_ENABLE_COLORBAR:
enableColorBars((Bool)param);
break;
case ADV7123_LOAD_CURSOR:/* load hardware cursor */
break;
case ADV7123_LOAD_LUT: /* load look-up table */
break;
}
return EDC_SUCCESS;
}
/*
* ======== ADV7123_open ========
*/
static EDC_Handle ADV7123_open(String devName, Arg optArg)
{
return (EDC_Handle)_ADV7123_IICADDR;
}
/**************************************************************************/
/* End of file */
/**************************************************************************/
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