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📄 vt1420.gel

📁 DSP/BIOS Driver Developer Kit 1.11 The DSP/BIOS Driver Developer Kit (DDK) provides a selection of
💻 GEL
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/*--------------------------------------------------------------*/
/* VT1420.gel                                                   */
/* version xxxx                                                 */
/*                                                              */
/* This GEL file is designed to be used in conjunction with the */
/* CCS 2.0 and the VT-142x TMS320C6416 DSP based PMC modules.   */
/* Copied from the TI TEB_6416.gel.                             */
/*                                                              */
/* Things to do:                                                */
/*     LED on/off func like LED_cycle()                         */
/*     Memory/config detect: Read GPIO, test memory, determine  */
/*                           Flash type (AMD vs SST) like       */
/*                                     QuickTest()              */
/*--------------------------------------------------------------*/

/*--------------------------------------------------------------*/
/* The StartUp() function is called each time CCS is started.   */
/* Customize this function to perform desired initialization.   */
/*--------------------------------------------------------------*/

StartUp()
{
/*  setup_memory_map();  */
  GEL_Reset();  
  init_emif();
  init_GPIO();
} 


/*--------------------------------------------------------------*/
/* The setup_memory_map() function does not appear to work in   */
/* the simulator.  It code be unnecessary since C64x only has   */
/* one mapping (unlike other TI DSPs).                          */
/*--------------------------------------------------------------*/
setup_memory_map()
{
        GEL_MapOn();
        GEL_MapReset();
        GEL_MapAdd(0x00000000, 0, 0x00100000, 1, 1); /* Internal Memory       */
        GEL_MapAdd(0x01800000, 0, 0x00000054, 1, 1); /* EMIFA CTL REGS        */
        GEL_MapAdd(0x01840000, 0, 0x000082FC, 1, 1); /* INT MEM CTL REGS      */
        GEL_MapAdd(0x018C0000, 0, 0x0000003C, 1, 1); /* MCBSP0 CTL REGS       */
        GEL_MapAdd(0x01900000, 0, 0x0000003C, 1, 1); /* MCBSP1 CTL REGS       */
        GEL_MapAdd(0x01940000, 0, 0x00000008, 1, 1); /* TIMER0 CTL REGS       */
        GEL_MapAdd(0x01980000, 0, 0x00000008, 1, 1); /* TIMER1 CTL REGS       */
        GEL_MapAdd(0x019C0000, 0, 0x00000008, 1, 1); /* INT CTL REGS          */
        GEL_MapAdd(0x01A00000, 0, 0x0000FFFC, 1, 1); /* EDMA REGS AND PARAM   */
        GEL_MapAdd(0x01A40000, 0, 0x0000003C, 1, 1); /* MCBSP2 CTL REGS       */
        GEL_MapAdd(0x01A80000, 0, 0x00000054, 1, 1); /* EMIFB CTL REGS        */
        GEL_MapAdd(0x01AC0000, 0, 0x00000008, 1, 1); /* TIMER2 CTL REGS       */
        GEL_MapAdd(0x01B00000, 0, 0x00000024, 1, 1); /* GPIO REGS             */
        GEL_MapAdd(0x02000000, 0, 0x00000030, 1, 1); /* QDMA REGS             */
        GEL_MapAdd(0x30000000, 0, 0x04000000, 1, 1); /* MCBSP0 Data, EDMA map */
        GEL_MapAdd(0x34000000, 0, 0x04000000, 1, 1); /* MCBSP1 Data, EDMA map */
        GEL_MapAdd(0x38000000, 0, 0x04000000, 1, 1); /* MCBSP2 Data, EDMA map */
        GEL_MapAdd(0x64000000, 0, 0x00040000, 1, 1); /* FLASH EMIF-B, CE1     */
        GEL_MapAdd(0x80000000, 0, 0x01000000, 1, 1); /* 16MB SDRAM EMIF-A, CE0*/
}

/*--------------------------------------------------------------*/
/* init_emif()                                                      */
/*             EMIF settings depend on EMIF Clock freq and      */
/*                     memory device specifics.                 */
/*                                                              */
/*             SDRAM devices: MT48LC2M32B2-7                    */
/*                            2Mx32, 512Kx32x4 banks            */
/*                            tRC(-7) = 70 nsec                 */
/*                            tRP(-7) = 20 nsec                 */
/*                            tRCD(-7) = 20 nsec                */
/*                            tREF(-7) = 64 msec for 4,096 rows */
/*                            tCL = 2 tcyc (min) for <=100MHz   */
/*                            tRAS(-7) = 42(min)-120K(max)nsec  */
/*                            tRRD(-7) = 14 nsec                */
/*                            tWR(-7) = 1 tcyc + 7 nsec (17min) */
/*                               min for the following=         */
/*                                    tRC for same bank         */
/*                                    tRRD for different banks  */
/*                            tRD2RD(-7) = 1 tcyc (figure 8)    */
/*                            tRD2DEAC(-7) = 2 tcyc (p 17)      */
/*                            tRD2WR(-7) = 1 tcyc (fig 9)       */
/*                            tR2WDQM(-7) = 2 tcyc (p 16)       */
/*                            tWR2WR(-7) = 1 tcyc (p 19)        */
/*                            tWR2DEAC(-7) = 2 tcyc (p 20)      */
/*                            tWR2RD(-7) = 1 tcyc (p 20)        */
/*                                                              */
/*                                                              */
/*                                                              */
/*             EMIFA Clock: 100MHz  (10 nsec tcyc)              */ 
/*                          33MHz DSP input clock               */
/*                          CPU=400MHz (x12 multiplier)         */
/*                          EMIFA clock boot settings: 01 CPU/4 */
/*                            :AECLKIN_SELECT = CPU/4 = 100MHz  */
/*                          Notes: VT-1420 uses ECLKOUT2        */
/*                                 DSP EMIF timing is based on  */
/*                                    ECLKOUT1 for tcyc         */
/*                                                              */
/*--------------------------------------------------------------*/
init_emif()
{

#define EMIFA_GCTL       0x01800000
#define EMIFA_CE1        0x01800004
#define EMIFA_CE0        0x01800008
#define EMIFA_CE2        0x01800010
#define EMIFA_CE3        0x01800014
#define EMIFA_SDRAMCTL   0x01800018
#define EMIFA_SDRAMREF   0x0180001c
#define EMIFA_SDRAMEXT   0x01800020
#define EMIFA_CE1SECCTL  0x01800044
#define EMIFA_CE0SECCTL  0x01800048
#define EMIFA_CE2SECCTL  0x01800050
#define EMIFA_CE3SECCTL  0x01800054

#define EMIFB_GCTL       0x01A80000
#define EMIFB_CE1        0x01A80004
#define EMIFB_CE0        0x01A80008
#define EMIFB_CE2        0x01A80010
#define EMIFB_CE3        0x01A80014
#define EMIFB_SDRAMCTL   0x01A80018
#define EMIFB_SDRAMREF   0x01A8001c
#define EMIFB_SDRAMEXT   0x01A80020
#define EMIFB_CE1SECCTL  0x01A80044
#define EMIFB_CE0SECCTL  0x01A80048
#define EMIFB_CE2SECCTL  0x01A80050
#define EMIFB_CE3SECCTL  0x01A80054
        
    /* EMIFA Control */
        *(int *)EMIFA_GCTL     = 0x000120DC; /* Why did TEB board write a '1' to bit 12? */
        
        /*EMIFA CE0 SDRAM*/
        *(int *)EMIFA_CE0      = 0xffffffdf;
        *(int *)EMIFA_SDRAMCTL = 0x47116000; /* Pure coincedence that this matches the TEB */
        *(int *)EMIFA_SDRAMREF = 0x000005DC; /* Use powerup default, more conservative than TEB */
        *(int *)EMIFA_SDRAMEXT = 0x000504A8; /* TEB value of 0x00054549 is more conservative */
                                             /* I thought it should be 0x000504A8 */
        

    /* EMIFB Control */
        *(int *)EMIFB_GCTL     = 0x000120DC; 
        
        /*EMIFB CE1 FLASH, 8 Bit*/
        *(int *)EMIFB_CE1      = 0xffffff03; /* Conservative #, Optimize speed by trying VT-1402 number 0x2372CD23 */

        *(int *)EMIFA_SDRAMCTL = 0x47116000; /* Do this again to reset the SDRAM */

}
 
/*--------------------------------------------------------------*/
/* GPIO DEFINITIONS, 1=Enable, 1=Output DIR                     */
/*--------------------------------------------------------------*/
#define GPEN_REG       0x01B00000
#define GPDIR_REG      0x01B00004
#define GPVAL_REG      0x01B00008

#define MS_FLASH       0x0001
#define GREEN_LED      0x0002
#define RED_LED        0x0004
#define MCBSP2_EN      0x0008
#define EXT_INT4       0x0010
#define EXT_INT5       0x0020
#define EXT_INT6       0x0040
#define DSP_ID         0x0080

#define Get_GPIO_En     (*(char *)GPEN_REG )
#define Get_GPIO_Val    (*(char *)GPVAL_REG )
#define Get_DSP_ID      ( (*(char *)GPVAL_REG & DSP_ID) >> 7 )
#define Get_GREEN_LED   ( (*(char *)GPVAL_REG & GREEN_LED) >> 1 )
#define Get_RED_LED     ( (*(char *)GPVAL_REG & RED_LED) >> 2 )


/*--------------------------------------------------------------*/
/* Timer GPIO DEFINITIONS, 1=Enable, 1=Output DIR               */
/*--------------------------------------------------------------*/
#define T0_CTL_REG       0x01940000
#define T1_CTL_REG       0x01980000
#define T1_CTL_REG       0x01AC0000
 
#define TIMER_CTL_DEF    0x00000000

#define TIMER_DIN        0x0004
#define TIMER_DOUT       0x0008

#define Get_DSP_Cfg0    ( (*(char *)T0_CTL_REG & TIMER_DIN) >> 2 )
#define Get_DSP_Cfg1    ( (*(char *)T1_CTL_REG & TIMER_DIN) >> 2 )


/*--------------------------------------------------------------*/
/* init_GPIO()                                                  */
/*--------------------------------------------------------------*/
init_GPIO()
{
/*    *(char *)GPEN_REG = Get_GPIO_En | (GREEN_LED | RED_LED | DSP_ID) ; */
        *(char *)GPEN_REG = 0x0 | (GREEN_LED | RED_LED | DSP_ID) ; 
        *(char *)GPDIR_REG = 0x0 | (GREEN_LED | RED_LED) ; 

}


/*--------------------------------------------------------------*/
/* clear_memory_map()                                           */
/*--------------------------------------------------------------*/
clear_memory_map()
{
    GEL_MapOff();
}

/*--------------------------------------------------------------*/
/* LED_cycle()                                                  */
/*--------------------------------------------------------------*/
LED_cycle()
{

  RED_LED_off();
  GREEN_LED_off();
  RED_LED_on();
  GREEN_LED_on();
  RED_LED_off();

}  


/*--------------------------------------------------------------*/
/* RED_LED_on()   logic low puts the LED on                     */
/*--------------------------------------------------------------*/
RED_LED_on()
{
    *(char *)GPVAL_REG = Get_GPIO_Val & ~RED_LED        ;
}  

/*--------------------------------------------------------------*/
/* RED_LED_off()                                                */
/*--------------------------------------------------------------*/
RED_LED_off()
{
    *(char *)GPVAL_REG = Get_GPIO_Val | RED_LED ;
}  

/*--------------------------------------------------------------*/
/* GREEN_LED_on()                                               */
/*--------------------------------------------------------------*/
GREEN_LED_on()
{
    *(char *)GPVAL_REG = Get_GPIO_Val & ~ GREEN_LED     ;
}  

/*--------------------------------------------------------------*/
/* GREEN_LED_off()                                               */
/*--------------------------------------------------------------*/
GREEN_LED_off()
{
    *(char *)GPVAL_REG = Get_GPIO_Val | GREEN_LED ;
}  



/*--------------------------------------------------------------*/
/* OnReset()                                                    */
/*--------------------------------------------------------------*/
OnReset(int nErrorCode)
{
        init_GPIO();
    LED_cycle();
        
        GEL_BreakPtReset();
        FlushCache();
        init_emif();
}


/*--------------------------------------------------------------*/
/* OnPreFileLoaded()                                            */
/* This function is called automatically when the 'Load Program'*/
/* Menu item is selected.                                       */
/*--------------------------------------------------------------*/
OnPreFileLoaded()
{
        FlushCache();
}

/*--------------------------------------------------------------*/
/* FlushCache()                                                 */
/*--------------------------------------------------------------*/ 
FlushCache()   
{ 
        *(int *)0x01840000 = (*(int *)0x01840000 | 0x00000300);
        *(int *)0x01845000 = 0x1;
}   


/*--------------------------------------------------------------*/
/* RESET MENU                                                   */
/*--------------------------------------------------------------*/ 
menuitem "Resets";

hotmenu Reset_BreakPts_and_EMIF()
{
        GEL_BreakPtReset();
        GEL_Reset();
        init_emif();
} 
hotmenu Flush_Cache() 
{ 
        FlushCache();
} 

/*--------------------------------------------------------------*/
/* MEMORY MAP MENU                                              */
/*--------------------------------------------------------------*/ 
menuitem "Memory Map";

hotmenu SetMemoryMap()
{
        setup_memory_map();
}

hotmenu ClearMemoryMap()
{
        clear_memory_map();
}

/*--------------------------------------------------------------*/
/* Quick Test MENU                                              */
/*--------------------------------------------------------------*/ 
menuitem "Check VT-1420";
hotmenu QuickTest()
{
        LED_cycle();
        LED_cycle();
        LED_cycle();
        GEL_OpenWindow("VT1420 Output", 0, 5);
        GEL_TextOut(" DSP_ID (0 for DSP A, 1 for DSP B): %d \n",
                      "VT1420 Output",1,1,1,
                      Get_DSP_ID);      
        GEL_TextOut(" DSP_CFG0 (expect=0): %d \n",
                      "VT1420 Output",1,1,1,
                      Get_DSP_Cfg0);    
        GEL_TextOut(" DSP_CFG1 (expect=0): %d \n",
                      "VT1420 Output",1,1,1,
                      Get_DSP_Cfg1);    
        GEL_TextOut(" GREEN LED (0=ON, 1=OFF): %d \n",
                      "VT1420 Output",1,1,1,
                      Get_GREEN_LED);   
        GEL_TextOut(" RED LED (0=ON, 1=OFF): %d \n\n",
                      "VT1420 Output",1,1,1,
                      Get_RED_LED);     

}

hotmenu REDLED_ON()
{
  RED_LED_on();
}

hotmenu REDLED_OFF()
{
  RED_LED_off();
}

hotmenu GREENLED_ON()
{
  GREEN_LED_on();
}

hotmenu GREENLED_OFF()
{
  GREEN_LED_off();
}

hotmenu CYCLE_LEDS()
{
  LED_cycle();
}

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