📄 vc5402.h
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/* File: vc5402.h */
/* Include file with CPU/Periperal register declarations */
//C54x CPU Memory-Mapped Registers
#define DSP_IMR (VUBYTE*)0x0000 //Interrupt mask register
#define DSP_IFR (VUBYTE*)0x0001 //Interrupt flag register
// 0002H~0005H Reserved
#define DSP_ST0 (VUBYTE*)0x0006 //Status 0 register
#define DSP_ST1 (VUBYTE*)0x0007 //Status 1 register
#define DSP_AL (VUBYTE*)0x0008 //A accumulator low (A [15:0])
#define DSP_AH (VUBYTE*)0x0009 //A accumulator high (A [31:16])
#define DSP_AG (VUBYTE*)0x000A //A accumulator guard (A [39:32])
#define DSP_BL (VUBYTE*)0x000B //B accumulator low (B [15:0])
#define DSP_BH (VUBYTE*)0x000C //B accumulator high (B [31:16])
#define DSP_BG (VUBYTE*)0x000D //B accumulator guard (B [39:32])
#define DSP_TREG (VUBYTE*)0x000E //Temporary register
#define DSP_TRN (VUBYTE*)0x000F //Transition register
#define DSP_AR0 (VUBYTE*)0x0010 //Auxiliary register 0
#define DSP_AR1 (VUBYTE*)0x0011 //Auxiliary register 1
#define DSP_AR2 (VUBYTE*)0x0012 //Auxiliary register 2
#define DSP_AR3 (VUBYTE*)0x0013 //Auxiliary register 3
#define DSP_AR4 (VUBYTE*)0x0014 //Auxiliary register 4
#define DSP_AR5 (VUBYTE*)0x0015 //Auxiliary register 5
#define DSP_AR6 (VUBYTE*)0x0016 //Auxiliary register 6
#define DSP_AR7 (VUBYTE*)0x0017 //Auxiliary register 7
#define DSP_SP (VUBYTE*)0x0018 //Stack pointer register
#define DSP_BK (VUBYTE*)0x0019 //Circular size register
#define DSP_BRC (VUBYTE*)0x001A //Block repeat counter
#define DSP_RSA (VUBYTE*)0x001B //Block repeat start address
#define DSP_REA (VUBYTE*)0x001C //Block repeat end address
#define DSP_PMST (VUBYTE*)0x001D //Processor mode status (PMST) register
#define DSP_XPC (VUBYTE*)0x001E //Extended memory map register
//#define Reserved1 0x001FH
//VC5402 McBSP Memory-Mapped register declarations
#define DSP_DRR20 (VUBYTE*)0x0020 //McBSP0 data receive register 2
#define DSP_DRR10 (VUBYTE*)0x0021 //McBSP0 data receive register 1
#define DSP_DXR20 (VUBYTE*)0x0022 //McBSP0 data transmit register 2
#define DSP_DXR10 (VUBYTE*)0x0023 //McBSP0 data transmit register 1
#define DSP_SPSA0 (VUBYTE*)0x0038 //McBSP0 serial port sub-bank address register
#define DSP_SPSD0 (VUBYTE*)0x0039 //McBSP0 serial port sub-bank data register
#define DSP_DRR21 (VUBYTE*)0x0040 //McBSP1 data receive register 2
#define DSP_DRR11 (VUBYTE*)0x0041 //McBSP1 data receive register 1
#define DSP_DXR21 (VUBYTE*)0x0042 //McBSP1 data transmit register 2
#define DSP_DXR11 (VUBYTE*)0x0043 //McBSP1 data transmit register 1
#define DSP_SPSA1 (VUBYTE*)0x0048 //McBSP1 serial port sub-bank address register
#define DSP_SPSD1 (VUBYTE*)0x0049 //McBSP1 serial port sub-bank data register
//VC5402 McBSP Control Register Sub-Address
#define DSP_SPCR10 0x0000 //Serial port control register 1
#define DSP_SPCR20 0x0001 //Serial port control register 2
#define DSP_RCR10 0x0002 //Receive control register 1
#define DSP_RCR20 0x0003 //Receive control register 2
#define DSP_XCR10 0x0004 //Transmit control register 1
#define DSP_XCR20 0x0005 //Transmit control register 2
#define DSP_SRGR10 0x0006 //Sample rate generator register 1
#define DSP_SRGR20 0x0007 //Sample rate generator register 2
#define DSP_MCR10 0x0008 //Multichannel register 1
#define DSP_MCR20 0x0009 //Multichannel register 2
#define DSP_RCERA0 0x000A //Receive channel enable register partition A
#define DSP_RCERB0 0x000B //Receive channel enable register partition B
#define DSP_XCERA0 0x000C //Transmit channel enable register partition A
#define DSP_XCERB0 0x000D //Transmit channel enable register partition B
#define DSP_PCR0 0x000E //Pin control register
//VC5402 Timer Memory-Mapped register declarations
#define DSP_TIM (VUBYTE*)0x0024 //Timer0 register
#define DSP_PRD (VUBYTE*)0x0025 //Timer0 period register
#define DSP_TCR (VUBYTE*)0x0026 //Timer0 control register
#define DSP_TIM1 (VUBYTE*)0x0030 //Timer1 register
#define DSP_PRD1 (VUBYTE*)0x0031 //Timer1 period register
#define DSP_TCR1 (VUBYTE*)0x0032 //Timer1 control register
//VC5402 Software Wait-State Control Register
#define DSP_SWWSR (VUBYTE*)0x0028 //Software Wait-State Register
#define DSP_BSCR (VUBYTE*)0x0029 //Bank-Switching Control Register
#define DSP_SWCR (VUBYTE*)0x002B //Software Wait-State Control Register
#define DSP_HPIC (VUBYTE*)0x002C //HPI control register
//VC5402 General Purpose I/O Control register declarations
#define DSP_GPIOCR (VUBYTE*)0x003C //General purpose I/O pins control register
#define DSP_GPIOSR (VUBYTE*)0x003D //General purpose I/O pins status register
//VC5402 DMA Memory-Mapped register declarations
#define DSP_DMPREC (VUBYTE*)0x0054 //DMA channel priority and enable control register
#define DSP_DMSA (VUBYTE*)0x0055 //DMA sub-bank address register
#define DSP_DMSDI (VUBYTE*)0x0056 //DMA sub-bank data register with sub-bank address auto-increment
#define DSP_DMSDN (VUBYTE*)0x0057 //DMA sub-bank data register
//VC5402 DMA Control Register Sub-Address
#define DSP_DMSRC0 0x0000 //DMA channel 0 source address register
#define DSP_DMDST0 0x0001 //DMA channel 0 destination address register
#define DSP_DMCTR0 0x0002 //DMA channel 0 element count register
#define DSP_DMSFC0 0x0003 //DMA channel 0 sync select and frame count register
#define DSP_DMMCR0 0x0004 //DMA channel 0 transfer mode control register
#define DSP_DMSRC1 0x0005 //DMA channel 1 source address register
#define DSP_DMDST1 0x0006 //DMA channel 1 destination address register
#define DSP_DMCTR1 0x0007 //DMA channel 1 element count register
#define DSP_DMSFC1 0x0008 //DMA channel 1 sync select and frame count register
#define DSP_DMMCR1 0x0009 //DMA channel 1 transfer mode control register
#define DSP_DMSRC2 0x000A //DMA channel 2 source address register
#define DSP_DMDST2 0x000B //DMA channel 2 destination address register
#define DSP_DMCTR2 0x000C //DMA channel 2 element count register
#define DSP_DMSFC2 0x000D //DMA channel 2 sync select and frame count register
#define DSP_DMMCR2 0x000E //DMA channel 2 transfer mode control register
#define DSP_DMSRC3 0x000F //DMA channel 3 source address register
#define DSP_DMDST3 0x0010 //DMA channel 3 destination address register
#define DSP_DMCTR3 0x0011 //DMA channel 3 element count register
#define DSP_DMSFC3 0x0012 //DMA channel 3 sync select and frame count register
#define DSP_DMMCR3 0x0013 //DMA channel 3 transfer mode control register
#define DSP_DMSRC4 0x0014 //DMA channel 4 source address register
#define DSP_DMDST4 0x0015 //DMA channel 4 destination address register
#define DSP_DMCTR4 0x0016 //DMA channel 4 element count register
#define DSP_DMSFC4 0x0017 //DMA channel 4 sync select and frame count register
#define DSP_DMMCR4 0x0018 //DMA channel 4 transfer mode control register
#define DSP_DMSRC5 0x0019 //DMA channel 5 source address register
#define DSP_DMDST5 0x001A //DMA channel 5 destination address register
#define DSP_DMCTR5 0x001B //DMA channel 5 element count register
#define DSP_DMSFC5 0x001C //DMA channel 5 sync select and frame count register
#define DSP_DMMCR5 0x001D //DMA channel 5 transfer mode control register
#define DSP_DMSRCP 0x001E //DMA source program page address (common channel)
#define DSP_DMDSTP 0x001F //DMA destination program page address (common channel)
#define DSP_DMIDX0 0x0020 //DMA element index address register 0
#define DSP_DMIDX1 0x0021 //DMA element index address register 1
#define DSP_DMFRI0 0x0022 //DMA frame index register 0
#define DSP_DMFRI1 0x0023 //DMA frame index register 1
#define DSP_DMGSA 0x0024 //DMA global source address reload register
#define DSP_DMGDA 0x0025 //DMA global destination address reload register
#define DSP_DMGCR 0x0026 //DMA global count reload register
#define DSP_DMGFR 0x0027 //DMA global frame count reload register
#define DSP_CLKMD (VUBYTE*)0x0058 //clock mode register
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