📄 uart.lst
字号:
000000C8 E5911000 LDR R1,[R1,#0x0] ; s_first0
000000CC E1A03001 MOV R3,R1
000000D0 E5102000 LDR R2,=SendBuf0 ; SendBuf0
000000D4 E7D23003 LDRB R3,[R2,+R3]
000000D8 E5102000 LDR R2,=0xE000C000
000000DC E5C23000 STRB R3,[R2,#0x0]
215: if(++s_first0 >= SEND_BUF_LEN)
000000E0 E5102000 LDR R2,=s_first0 ; s_first0
000000E4 E2811001 ADD R1,R1,#0x0001
000000E8 E5821000 STR R1,[R2,#0x0] ; s_first0
000000EC E3510C02 CMP R1,#0x0200
000000F0 3A000002 BCC L_59 ; Targ=0x100
216: s_first0 = 0;
000000F4 E3A02000 MOV R2,#0x0
000000F8 E5101000 LDR R1,=s_first0 ; s_first0
000000FC E5812000 STR R2,[R1,#0x0] ; s_first0
217: }
00000100 L_59:
00000100 E5101000 LDR R1,=s_first0 ; s_first0
00000104 E5912000 LDR R2,[R1,#0x0] ; s_first0
00000108 E5101000 LDR R1,=s_next0 ; s_next0
0000010C E5911000 LDR R1,[R1,#0x0] ; s_next0
00000110 E1510002 CMP R1,R2
00000114 0A000003 BEQ L_60 ; Targ=0x128
00000118 E1A01000 MOV R1,R0 ; nCnt
0000011C E2410001 SUB R0,R1,#0x0001 ; nCnt
00000120 E3510000 CMP R1,#0x0000 ; nCnt
00000124 1AFFFFE6 BNE L_61 ; Targ=0xC4
00000128 L_60:
00000128 ; SCOPE-END
219: break;
ARM COMPILER V2.53, uart 09/06/07 15:43:41 PAGE 14
00000128 EAFFFFB5 B L_45 ; Targ=0x4
223: }
0000012C L_44:
225: VICVectAddr=0;
0000012C E3A01000 MOV R1,#0x0
00000130 E5100000 LDR R0,=0xFFFFF030
00000134 E5801000 STR R1,[R0,#0x0]
00000138 ; SCOPE-END
226: }
00000138 E8BD001F LDMIA R13!,{R0-R4}
0000013C E25EF004 SUBS R15,R14,#0x0004
00000140 ENDP ; 'Uart0_irq?A'
*** CODE SEGMENT '?PR?Uart1_irq?A?uart':
228: void Uart1_irq(void) __irq
00000000 E92D001F STMDB R13!,{R0-R4}
229: {
00000004 ; SCOPE-START
231: while(1) // 循环处理,直到UART1中无任何挂起的中断
00000004 L_67:
233: if((iir = U1IIR) & 1)
00000004 E5100000 LDR R0,=0xE0010008
00000008 E5900000 LDR R0,[R0,#0x0]
0000000C E1A00C00 MOV R0,R0,LSL #24
00000010 E1A00C20 MOV R0,R0,LSR #24
00000014 E1A01000 MOV R1,R0 ; iir
00000018 ---- Variable 'iir' assigned to Register 'R1' ----
00000018 E1A00C00 MOV R0,R0,LSL #24
0000001C E1A00C20 MOV R0,R0,LSR #24
00000020 E3100001 TST R0,#0x0001
00000024 1A000040 BNE L_66 ; Targ=0x12C
235: switch(iir & 0x0e)
00000028 E1A00001 MOV R0,R1 ; iir
0000002C E1A00C00 MOV R0,R0,LSL #24 ; iir
00000030 E1A00C20 MOV R0,R0,LSR #24
00000034 E200000E AND R0,R0,#0x000E
00000038 E3500002 CMP R0,#0x0002
0000003C 0A00001E BEQ L_71 ; Targ=0xBC
00000040 E350000C CMP R0,#0x000C
00000044 0A000001 BEQ L_78 ; Targ=0x50
00000048 E3500004 CMP R0,#0x0004
0000004C 1AFFFFEC BNE L_67 ; Targ=0x4
239: while(U1LSR & 1) //将fifo中的所有数据读完
00000050 L_78:
00000050 EA000014 B L_75 ; Targ=0xA8
00000054 L_77:
241: ch = U1RBR;
00000054 E5100000 LDR R0,=0xE0010000
00000058 E5D04000 LDRB R4,[R0,#0x0]
0000005C ---- Variable 'ch' assigned to Register 'R4' ----
242: if(r_next1 != r_first1-1)
0000005C E5100000 LDR R0,=r_first1 ; r_first1
00000060 E5901000 LDR R1,[R0,#0x0] ; r_first1
00000064 E2411001 SUB R1,R1,#0x0001
00000068 E5100000 LDR R0,=r_next1 ; r_next1
0000006C E5900000 LDR R0,[R0,#0x0] ; r_next1
00000070 E1500001 CMP R0,R1
00000074 0A00000B BEQ L_75 ; Targ=0xA8
244: RcvBuf1[r_next1] = ch;
00000078 E1A01004 MOV R1,R4 ; ch
0000007C E1A03000 MOV R3,R0
00000080 E5102000 LDR R2,=RcvBuf1 ; RcvBuf1
00000084 E7C21003 STRB R1,[R2,+R3]
245: if (++r_next1 >= RCV_BUF_LEN)
00000088 E5101000 LDR R1,=r_next1 ; r_next1
0000008C E2800001 ADD R0,R0,#0x0001
00000090 E5810000 STR R0,[R1,#0x0] ; r_next1
ARM COMPILER V2.53, uart 09/06/07 15:43:41 PAGE 15
00000094 E3500B01 CMP R0,#0x0400
00000098 3A000002 BCC L_75 ; Targ=0xA8
246: r_next1 = 0;
0000009C E3A01000 MOV R1,#0x0
000000A0 E5100000 LDR R0,=r_next1 ; r_next1
000000A4 E5801000 STR R1,[R0,#0x0] ; r_next1
248: }
000000A8 L_75:
000000A8 E5100000 LDR R0,=0xE0010014
000000AC E5D00000 LDRB R0,[R0,#0x0]
000000B0 E3100001 TST R0,#0x0001
000000B4 1AFFFFE6 BNE L_77 ; Targ=0x54
249: break;
000000B8 EAFFFFD1 B L_67 ; Targ=0x4
251: case 0x02: // THR Empty.
000000BC L_71:
252: {
000000BC ; SCOPE-START
253: DWORD nCnt = 16; //fifo counter
000000BC E3A00010 MOV R0,#0x10
000000C0 ---- Variable 'nCnt' assigned to Register 'R0' ----
254: while( s_next1 != s_first1 && nCnt--)
000000C0 EA00000E B L_81 ; Targ=0x100
000000C4 L_83:
256: U1THR = SendBuf1[s_first0];
000000C4 E5101000 LDR R1,=s_first0 ; s_first0
000000C8 E5912000 LDR R2,[R1,#0x0] ; s_first0
000000CC E5101000 LDR R1,=SendBuf1 ; SendBuf1
000000D0 E7D12002 LDRB R2,[R1,+R2]
000000D4 E5101000 LDR R1,=0xE0010000
000000D8 E5C12000 STRB R2,[R1,#0x0]
257: if(++s_first1 >= SEND_BUF_LEN)
000000DC E5102000 LDR R2,=s_first1 ; s_first1
000000E0 E5921000 LDR R1,[R2,#0x0] ; s_first1
000000E4 E2811001 ADD R1,R1,#0x0001
000000E8 E5821000 STR R1,[R2,#0x0] ; s_first1
000000EC E3510C02 CMP R1,#0x0200
000000F0 3A000002 BCC L_81 ; Targ=0x100
258: s_first1 = 0;
000000F4 E3A02000 MOV R2,#0x0
000000F8 E5101000 LDR R1,=s_first1 ; s_first1
000000FC E5812000 STR R2,[R1,#0x0] ; s_first1
259: }
00000100 L_81:
00000100 E5101000 LDR R1,=s_first1 ; s_first1
00000104 E5912000 LDR R2,[R1,#0x0] ; s_first1
00000108 E5101000 LDR R1,=s_next1 ; s_next1
0000010C E5911000 LDR R1,[R1,#0x0] ; s_next1
00000110 E1510002 CMP R1,R2
00000114 0A000003 BEQ L_82 ; Targ=0x128
00000118 E1A01000 MOV R1,R0 ; nCnt
0000011C E2410001 SUB R0,R1,#0x0001 ; nCnt
00000120 E3510000 CMP R1,#0x0000 ; nCnt
00000124 1AFFFFE6 BNE L_83 ; Targ=0xC4
00000128 L_82:
00000128 ; SCOPE-END
261: break;
00000128 EAFFFFB5 B L_67 ; Targ=0x4
265: }
0000012C L_66:
267: VICVectAddr=0;
0000012C E3A01000 MOV R1,#0x0
00000130 E5100000 LDR R0,=0xFFFFF030
00000134 E5801000 STR R1,[R0,#0x0]
00000138 ; SCOPE-END
268: }
ARM COMPILER V2.53, uart 09/06/07 15:43:41 PAGE 16
00000138 E8BD001F LDMIA R13!,{R0-R4}
0000013C E25EF004 SUBS R15,R14,#0x0004
00000140 ENDP ; 'Uart1_irq?A'
*** CODE SEGMENT '?PR?InitUart?T?uart':
277: void InitUart (void)
00000000 B570 PUSH {R4-R6,LR}
280: PINSEL0 = (PINSEL0 & (~0x0f000f)) | 0x050005; // set p0[1..0] for uart0
00000002 4800 LDR R0,=0xE002C000
00000004 6801 LDR R1,[R0,#0x0]
00000006 4800 LDR R0,=0xFFF0FFF0
00000008 4001 AND R1,R0
0000000A 4800 LDR R0,=0x50005
0000000C 4301 ORR R1,R0
0000000E 4800 LDR R0,=0xE002C000
00000010 6001 STR R1,[R0,#0x0]
282: ResetBufferPointer(0);
00000012 2000 MOV R0,#0x0
00000014 F7FF BL ResetBufferPointer?T ; T=0x0001 (1)
00000016 FFF4 BL ResetBufferPointer?T ; T=0x0001 (2)
283: ResetBufferPointer(1);
00000018 2001 MOV R0,#0x1
0000001A F7FF BL ResetBufferPointer?T ; T=0x0001 (1)
0000001C FFF1 BL ResetBufferPointer?T ; T=0x0001 (2)
285: U0LCR = 0x83; // 默认"9600,n,8,1"
0000001E 2683 MOV R6,#0x83
00000020 4800 LDR R0,=0xE000C00C
00000022 7006 STRB R6,[R0,#0x0]
286: SET_UART0_BAUD(9600)
00000024 2501 MOV R5,#0x1
00000026 4800 LDR R0,=0xE000C004
00000028 7005 STRB R5,[R0,#0x0]
0000002A 2486 MOV R4,#0x86
0000002C 4800 LDR R0,=0xE000C000
0000002E 7004 STRB R4,[R0,#0x0]
287: U0LCR = 0x03;
00000030 2303 MOV R3,#0x3
00000032 4800 LDR R0,=0xE000C00C
00000034 7003 STRB R3,[R0,#0x0]
288: U0IER = 0x03; // enable rx/tx interrupt.
00000036 2203 MOV R2,#0x3
00000038 4800 LDR R0,=0xE000C004
0000003A 6002 STR R2,[R0,#0x0]
289: U0FCR = 1 | (2<<6); // enable fifo,8 byte
0000003C 2181 MOV R1,#0x81
0000003E 4800 LDR R0,=0xE000C008
00000040 7001 STRB R1,[R0,#0x0]
291: U1LCR = 0x83; // 默认"9600,n,8,1"
00000042 4800 LDR R0,=0xE001000C
00000044 7006 STRB R6,[R0,#0x0]
292: SET_UART1_BAUD(9600)
00000046 4800 LDR R0,=0xE0010004
00000048 7005 STRB R5,[R0,#0x0]
0000004A 4800 LDR R0,=0xE0010000
0000004C 7004 STRB R4,[R0,#0x0]
293: U1LCR = 0x03;
0000004E 4800 LDR R0,=0xE001000C
00000050 7003 STRB R3,[R0,#0x0]
294: U1IER = 0x03; // enable rx/tx interrupt.
00000052 4800 LDR R0,=0xE0010004
00000054 6002 STR R2,[R0,#0x0]
295: U1FCR = 1 | (2<<6); // enable fifo,8 byte
00000056 4800 LDR R0,=0xE0010008
00000058 7001 STRB R1,[R0,#0x0]
298: VICVectAddr3 = (unsigned long)Uart0_irq;
0000005A 4900 LDR R1,=Uart0_irq?A ; Uart0_irq?A
0000005C 4800 LDR R0,=0xFFFFF10C
ARM COMPILER V2.53, uart 09/06/07 15:43:41 PAGE 17
0000005E 6001 STR R1,[R0,#0x0]
299: VICVectCntl3 = 0x20 | 6;
00000060 2126 MOV R1,#0x26
00000062 4800 LDR R0,=0xFFFFF20C
00000064 6001 STR R1,[R0,#0x0]
300: VICIntEnable = 1 << 6 ;
00000066 2140 MOV R1,#0x40
00000068 4800 LDR R0,=0xFFFFF010
0000006A 6001 STR R1,[R0,#0x0]
302: VICVectAddr4 = (unsigned long)Uart1_irq;
0000006C 4900 LDR R1,=Uart1_irq?A ; Uart1_irq?A
0000006E 4800 LDR R0,=0xFFFFF110
00000070 6001 STR R1,[R0,#0x0]
303: VICVectCntl4 = 0x20 | 7;
00000072 2127 MOV R1,#0x27
00000074 4800 LDR R0,=0xFFFFF210
00000076 6001 STR R1,[R0,#0x0]
304: VICIntEnable = 1 << 7 ;
00000078 2180 MOV R1,#0x80
0000007A 4800 LDR R0,=0xFFFFF010
0000007C 6001 STR R1,[R0,#0x0]
305: }
0000007E BC70 POP {R4-R6}
00000080 BC08 POP {R3}
00000082 4718 BX R3
00000084 ENDP ; 'InitUart?T'
Module Information Static
----------------------------------
code size = ------
data size = 3104
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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