cfg6713.h

TMS320C6713的语音信号的FIR滤波

#ifndef CFG_6713_
#define CFG_6713_

#ifdef __cplusplus
extern "C" {
#endif
//定义PLL端口初始化值
#define CSR_PLLEN       0x00000001
#define CSR_PLLPWRDN    0x00000002
#define CSR_PLLRST      0x00000008 
#define CSR_PLLSTABLE   0x00000040
#define DIV_ENABLE      0x00008000
//定义EMIF端口初始化值
#define EMIF_GCTL_VAL       0x00000078;
#define	EMIF_CE0_VAL        0xffffff93;  /* CE0 SDRAM                     */
#define	EMIF_CE1_VAL        0xffffff13;  /* CE1 Flash 16-bit               */
#define	EMIF_SDRAMCTL_VAL   0x53115000;  /* SDRAM control                 */
#define	EMIF_SDRAMTIM_VAL   0x00000578;  /* SDRAM timing (refresh)        */
#define	EMIF_SDRAMEXT_VAL   0x000a8529;

//定义MCBSP0端口初始化值
	
#define SPCR0_VAL	0x00004000
/*
	31------------16 15-------------0
;	000000~~~~~~~~~~ ~~~~~~~~~~~~~~~~b	reserved
;	~~~~~~0~~~~~~~~~ ~~~~~~~~~~~~~~~~b	FREE:  	FREE = 1, Free running mode is enabled
;	~~~~~~~0~~~~~~~~ ~~~~~~~~~~~~~~~~b	SOFT: 	Soft mode enabled
;	~~~~~~~~0~~~~~~~ ~~~~~~~~~~~~~~~~b	FRST_:	0, Frame sync generator is reset 
;	~~~~~~~~~0~~~~~~ ~~~~~~~~~~~~~~~~b	GRST_: 	0, Sample rate generator is reset
;	~~~~~~~~~~00~~~~ ~~~~~~~~~~~~~~~~b	XINTM: 	XINT driven by XRDY
;	~~~~~~~~~~~~0~~~ ~~~~~~~~~~~~~~~~b	XSYNCERR: Read Only
;	~~~~~~~~~~~~~0~~ ~~~~~~~~~~~~~~~~b	XEMPTY:	Read Only
;	~~~~~~~~~~~~~~0~ ~~~~~~~~~~~~~~~~b	XRDY: 	Read Only
;	~~~~~~~~~~~~~~~0 ~~~~~~~~~~~~~~~~b	XRST_: 	Transmitter is disabled and in reset state
;			 0~~~~~~~~~~~~~~~b	DLB:	Digital loopback mode is disabled
;			 ~10~~~~~~~~~~~~~b	RJUST:	Right-justify and zero-fill MSbs in DRR(1/2)
;			 ~~~00~~~~~~~~~~~b	CLKSTP:	Clock Stop Mode disabled   
;			 ~~~~~000~~~~~~~~b	reserved
;			 ~~~~~~~~0~~~~~~~b	DXENA:	DX enabler is off 
;	   		 ~~~~~~~~~0~~~~~~b	reserved
;	 		 ~~~~~~~~~~00~~~~b	RINTM: 	RINT driven by RRDY
;		 	 ~~~~~~~~~~~~0~~~b	RSYNCERR: Read Only
;			 ~~~~~~~~~~~~~0~~b	RFULL: 	Read Only
;			 ~~~~~~~~~~~~~~0~b	RRDY: 	Read Only
;			 ~~~~~~~~~~~~~~~0b	RRST_: 	Receiver is disabled and in reset state
bit 0 to bit 25
*/

#define RCR0_VAL		0x000503A0	
/*	
;	0~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b RPHASE:	single phase receive frame
;	~0000000~~~~~~~~ ~~~~~~~~~~~~~~~~b RFRLEN2:Receive frame length for phase 2 is RxHSTOPBITS
;	~~~~~~~~000~~~~~ ~~~~~~~~~~~~~~~~b RWDLEN2:Receive word length for phase 2 is 8 bits 
;	~~~~~~~~~~~00~~~ ~~~~~~~~~~~~~~~~b RCOMPAND:no companding, data transfer starts with MSb first
;	~~~~~~~~~~~~~1~~ ~~~~~~~~~~~~~~~~b RFIG:	ignore receive frame syncs after the first one
;	~~~~~~~~~~~~~~01 ~~~~~~~~~~~~~~~~b RDATDLY:1-bit delay between FSR and data
;			 0~~~~~~~~~~~~~~~b reserved
;			 ~0000011~~~~~~~~b RFRLEN1:Receive frame length for phase 1 is 1 words
;			 ~~~~~~~~101~~~~~b 16bit RWDLEN1:Receive word length for phase 1 is 16 bits	
;			 ~~~~~~~~~~~0~~~~b Receive 32 bit reversal feature 
			 ~~~~~~~~~~~~0000b reserved
*/

#define XCR0_VAL 0x00000000
/*
;	0~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b XPHASE:	sigle phase transmit frame
;	~0000000~~~~~~~~ ~~~~~~~~~~~~~~~~b XFRLEN2:Transmit frame length for phase 2 is TxHSTOPBITS words
;	~~~~~~~~000~~~~~ ~~~~~~~~~~~~~~~~b XWDLEN2:Transmit word length for phase 2 is 8 bits 
;	~~~~~~~~~~~00~~~ ~~~~~~~~~~~~~~~~b XCOMPAND:no companding, data transfer starts with MSb first
;	~~~~~~~~~~~~~0~~ ~~~~~~~~~~~~~~~~b XFIG:	ignore transmit frame syncs after the first one
;	~~~~~~~~~~~~~~01 ~~~~~~~~~~~~~~~~b XDATDLY:1-bit delay between FSX and data
;			 0~~~~~~~~~~~~~~~b reserved
;			 ~0000011~~~~~~~~b XFRLEN1:Transmit frame length for phase 1 is 4 words
;			 ~~~~~~~~010~~~~~b XWDLEN1:Transmit word length for phase 1 is 16 bits	
;			 ~~~~~~~~~~~00000b reserved

*/

#define SRGR0_VAL	0x20000000
/*
;	0~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b GSYNC:	sample rate generator clock (CLKG) is free running
;	~0~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b CLKSP:	unused
;	~~1~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b CLKSM:	Sample rate generator clock derived from CPU clock
;	~~~0~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b FSGM:	Transmit frame sync (FSX) due to DXR-to-XSR copy
;	~~~~111111111111 ~~~~~~~~~~~~~~~~b FPER:	Frame Period=4096
; 			 00000111~~~~~~~~b FWID:	Frame Width is 1 CLKG period
;			 ~~~~~~~~00001111b CLKGDV:	Sample rate generator clock divider=0Fh
*/	

#define RCER0_VAL	0x0FFFFFFFF//MCBSP receive channel enable regiser partition 
#define XCER0_VAL	0x0
#define MCR0_VAL		0x00000000

#define PCR0_VAL		0x00000001
/*
.word	15-------------0                  	
;	00~~~~~~~~~~~~~~b	reserved
;	~~0~~~~~~~~~~~~~b	XIOEN:	DR,CLKS not GPI; DX not GPO; FSX,CLKX not GPIO
;	~~~0~~~~~~~~~~~~b	RIOEN:	DR,CLKS not GPI; DX not GPO; FSR,CLKR not GPIO
;	~~~~1~~~~~~~~~~~b	FSXM:	Transmit frame sync determined by FSGM (in SRGR2)
;	~~~~~0~~~~~~~~~~b	FSRM:	Receive frame sync generated by external device (FSR is input)
;	~~~~~~1~~~~~~~~~b	CLKXM:	CLKX is output driven by internal sample rate generator
;	~~~~~~~0~~~~~~~~b	CLKRM:	CLKR is output driven by internal sample rate generator
;	~~~~~~~~0~~~~~~~b	reserved
;	~~~~~~~~~0~~~~~~b	CLKS_STAT: Read Only
;	~~~~~~~~~~0~~~~~b	DX_STAT:Read Only
;	~~~~~~~~~~~0~~~~b	DR_STAT:Read Only
;	~~~~~~~~~~~~0~~~b	FSXP:	FSX is active high
;	~~~~~~~~~~~~~0~~b	FSRP:	FSR is active high
;	~~~~~~~~~~~~~~0~b	CLKXP:	Transmit data sampled on rising edge of CLKX
;	~~~~~~~~~~~~~~~1b	CLKRP:	0=Receive data sampled on falling edge of CLKR	
*/

//************定义MCBSP1端口初始化值*******************/
#define SPCR1_VAL	0x03000000
/*
	31------------16 15-------------0
;	000000~~~~~~~~~~ ~~~~~~~~~~~~~~~~b	reserved
;	~~~~~~0~~~~~~~~~ ~~~~~~~~~~~~~~~~b	FREE:  	FREE = 1, Free running mode is enabled
;	~~~~~~~0~~~~~~~~ ~~~~~~~~~~~~~~~~b	SOFT: 	Soft mode enabled
;	~~~~~~~~0~~~~~~~ ~~~~~~~~~~~~~~~~b	FRST_:	0, Frame sync generator is reset 
;	~~~~~~~~~0~~~~~~ ~~~~~~~~~~~~~~~~b	GRST_: 	0, Sample rate generator is reset
;	~~~~~~~~~~00~~~~ ~~~~~~~~~~~~~~~~b	XINTM: 	XINT driven by XRDY
;	~~~~~~~~~~~~0~~~ ~~~~~~~~~~~~~~~~b	XSYNCERR: Read Only
;	~~~~~~~~~~~~~0~~ ~~~~~~~~~~~~~~~~b	XEMPTY:	Read Only
;	~~~~~~~~~~~~~~0~ ~~~~~~~~~~~~~~~~b	XRDY: 	Read Only
;	~~~~~~~~~~~~~~~0 ~~~~~~~~~~~~~~~~b	XRST_: 	Transmitter is disabled and in reset state
;			 0~~~~~~~~~~~~~~~b	DLB:	Digital loopback mode is disabled
;			 ~10~~~~~~~~~~~~~b	RJUST:	Right-justify and zero-fill MSbs in DRR(1/2)
;			 ~~~00~~~~~~~~~~~b	CLKSTP:	Clock Stop Mode disabled   
;			 ~~~~~000~~~~~~~~b	reserved
;			 ~~~~~~~~0~~~~~~~b	DXENA:	DX enabler is off 
;	   		 ~~~~~~~~~0~~~~~~b	reserved
;	 		 ~~~~~~~~~~00~~~~b	RINTM: 	RINT driven by RRDY
;		 	 ~~~~~~~~~~~~0~~~b	RSYNCERR: Read Only
;			 ~~~~~~~~~~~~~0~~b	RFULL: 	Read Only
;			 ~~~~~~~~~~~~~~0~b	RRDY: 	Read Only
;			 ~~~~~~~~~~~~~~~0b	RRST_: 	Receiver is disabled and in reset state
bit 0 to bit 25
*/

#define RCR1_VAL	0x000500A0	
/*	
;	0~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b RPHASE:	single phase receive frame
;	~0000000~~~~~~~~ ~~~~~~~~~~~~~~~~b RFRLEN2:Receive frame length for phase 2 is RxHSTOPBITS
;	~~~~~~~~000~~~~~ ~~~~~~~~~~~~~~~~b RWDLEN2:Receive word length for phase 2 is 8 bits 
;	~~~~~~~~~~~00~~~ ~~~~~~~~~~~~~~~~b RCOMPAND:no companding, data transfer starts with MSb first
;	~~~~~~~~~~~~~1~~ ~~~~~~~~~~~~~~~~b RFIG:ignore receive frame syncs after the first one
;	~~~~~~~~~~~~~~01 ~~~~~~~~~~~~~~~~b RDATDLY:1-bit delay between FSR and data
;			 0~~~~~~~~~~~~~~~b reserved
;			 ~0000000~~~~~~~~b RFRLEN1:Receive frame length for phase 1 is 1 words
;			 ~~~~~~~~101~~~~~b 16bit RWDLEN1:Receive word length for phase 1 is 16 bits	
;			 ~~~~~~~~~~~0~~~~b Receive 32 bit reversal feature 
			 ~~~~~~~~~~~~0000b reserved
*/

#define XCR1_VAL 0x000101a0
/*
;	0~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b XPHASE:	sigle phase transmit frame
;	~0000000~~~~~~~~ ~~~~~~~~~~~~~~~~b XFRLEN2:Transmit frame length for phase 2 is TxHSTOPBITS words
;	~~~~~~~~000~~~~~ ~~~~~~~~~~~~~~~~b XWDLEN2:Transmit word length for phase 2 is 8 bits 
;	~~~~~~~~~~~00~~~ ~~~~~~~~~~~~~~~~b XCOMPAND:no companding, data transfer starts with MSb first
;	~~~~~~~~~~~~~0~~ ~~~~~~~~~~~~~~~~b XFIG:ignore transmit frame syncs after the first one
;	~~~~~~~~~~~~~~01 ~~~~~~~~~~~~~~~~b XDATDLY:1-bit delay between FSX and data
;			 0~~~~~~~~~~~~~~~b reserved
;			 ~0000001~~~~~~~~b XFRLEN1:Transmit frame length for phase 1 is 4 words
;			 ~~~~~~~~101~~~~~b XWDLEN1:Transmit word length for phase 1 is 16 bits	
;			 ~~~~~~~~~~~00000b reserved

*/

#define SRGR1_VAL	0x2080037f
/*
;	0~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b GSYNC:	sample rate generator clock (CLKG) is free running
;	~0~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b CLKSP:	unused
;	~~1~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b CLKSM:	Sample rate generator clock derived from CPU clock
;	~~~1~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~b FSGM:	Transmit frame sync (FSX) due to DXR-to-XSR copy
;	~~~~000001000000 ~~~~~~~~~~~~~~~~b FPER:	Frame Period=4096
; 			 00000011~~~~~~~~b FWID:	Frame Width is 1 CLKG period
;			 ~~~~~~~~00001111b CLKGDV:	Sample rate generator clock divider=0Fh
*/	

#define RCER1_VAL	0x0//MCBSP receive channel enable regiser partition 
#define XCER1_VAL	0xffffffff//MCBSP transmit channel enable
#define MCR1_VAL	0x0
#define PCR1_VAL	0x0F00
/*
	15-------------0                  	
;	00~~~~~~~~~~~~~~b	reserved
;	~~0~~~~~~~~~~~~~b	XIOEN:	DR,CLKS not GPI; DX not GPO; FSX,CLKX not GPIO
;	~~~0~~~~~~~~~~~~b	RIOEN:	DR,CLKS not GPI; DX not GPO; FSR,CLKR not GPIO
;	~~~~1~~~~~~~~~~~b	FSXM:	Transmit frame sync determined by FSGM (in SRGR2)
;	~~~~~0~~~~~~~~~~b	FSRM:	Receive frame sync generated by external device (FSR is input)
;	~~~~~~1~~~~~~~~~b	CLKXM:	CLKX is output driven by internal sample rate generator
;	~~~~~~~0~~~~~~~~b	CLKRM:	CLKR is output driven by internal sample rate generator
;	~~~~~~~~0~~~~~~~b	reserved
;	~~~~~~~~~0~~~~~~b	CLKS_STAT: Read Only
;	~~~~~~~~~~0~~~~~b	DX_STAT:Read Only
;	~~~~~~~~~~~0~~~~b	DR_STAT:Read Only
;	~~~~~~~~~~~~0~~~b	FSXP:	FSX is active high
;	~~~~~~~~~~~~~0~~b	FSRP:	FSR is active high
;	~~~~~~~~~~~~~~0~b	CLKXP:	Transmit data sampled on rising edge of CLKX
;	~~~~~~~~~~~~~~~0b	CLKRP:	Receive data sampled on falling edge of CLKR	
*/


#ifdef __cplusplus
}
#endif

#endif