c6416h.h.bak

6416 emif flash 引导烧写程序

/*******************************************************************************
* FILENAME                        c6416.h
*
* DESCRIPTION
* 6416 Header File
*  September  2004  WangHui
*
*******************************************************************************/

/* Register definitions for C6416 chip  */

/* Define EMIF Registers  */
#define EMIFA_GBLCTL 	0x01800000	/* Address of EMIFA global control		*/
#define EMIFA_CE0		0x01800008	/* Address of EMIFA CE0 control			*/
#define EMIFA_CE1		0x01800004	/* Address of EMIFA CE1 control			*/
#define EMIFA_CE2		0x01800010	/* Address of EMIFA CE0 control			*/
#define EMIFA_CE3		0x01800014	/* Address of EMIFA CE1 control			*/
#define EMIFA_SDCTL		0x01800018	/* Address of EMIFA SDRAM control		*/
#define EMIFA_SDTIM		0x0180001c	/* Address of EMIFA SDRM refresh period	*/
#define EMIFA_SDEXT		0x01800020	/* Address of EMIFA SDRAM extension		*/
#define EMIFA_PDTCTL		0x01800040	/* Address of  PDT control	*/

#define EMIFA_CESEC0		0x01800048	/* Address of EMIFA CE0 secondary control			*/
#define EMIFA_CESEC1		0x01800044	/* Address of EMIFA CE1 secondary control			*/
#define EMIFA_CESEC2		0x01800050	/* Address of EMIFA CE0 secondary control			*/
#define EMIFA_CESEC3		0x01800054	/* Address of EMIFA CE1 secondary control			*/

#define EMIFB_GBLCTL 	0x01A00000	/* Address of EMIFA global control		*/
#define EMIFB_CE0		0x01A00008	/* Address of EMIFA CE0 control			*/
#define EMIFB_CE1		0x01A00004	/* Address of EMIFA CE1 control			*/
#define EMIFB_CE2		0x01A00010	/* Address of EMIFA CE0 control			*/
#define EMIFB_CE3		0x01A00014	/* Address of EMIFA CE1 control			*/
#define EMIFB_SDCTL		0x01A00018	/* Address of EMIFA SDRAM control		*/
#define EMIFB_SDTIM		0x01A0001c	/* Address of EMIFA SDRM refresh period	*/
#define EMIFB_SDEXT		0x01A00020	/* Address of EMIFA SDRAM extension		*/
#define EMIFB_PDTCTL		0x01A00040	/* Address of  PDT control	*/

#define EMIFB_CESEC0		0x01A00048	/* Address of EMIFA CE0 secondary control			*/
#define EMIFB_CESEC1		0x01A00044	/* Address of EMIFA CE1 secondary control			*/
#define EMIFB_CESEC2		0x01A00050	/* Address of EMIFA CE0 secondary control			*/
#define EMIFB_CESEC3		0x01A00054	/* Address of EMIFA CE1 secondary control			*/



#define FLASH_ADR1 0x9000aaaa
#define FLASH_ADR2 0x90005555

/**********************************************************************************
*GCR                R-0    R-0  R-0 R-0   R/W-0
*[31..16]|[15..12]|BUSREQ,ARDY,HOLD,HOLDA|NHOLD,RSV,EKEN,CLK1EN|CLK2EN,RSV,RSV,RSV
*-----------------------------------------------------------------------------------
* 0x0000   0x3    |   0    0    0     0  |   1   0    1     0  |  0     0   0   0
*NHOLD:0=NO hold is disabled. 1=No hold is enabled ,/hold input is ignored.
*EKEN=ECLKOUT is enabled to clock.
*CLK1EN=0 CLKOUT1 is held high.
*CLK2EN=0 CLKOUT2 is held high    
************************************************************************************/
#define GCR  0x000030a0

/**********************************************************************************
*CE0                R-0    R-0  R-0 R-0   R/W-0
*[31..28]|[27..22][21..20]|[19..16]|[15..14]|[13..8]|[7..4] | 3  [2..0]|
*-----------------------------------------------------------------------------------
* WRSETUP| WRSTRB   WRHLD |RDSETUP |   TA   | RDSTRB| MTYPE |RSV  RDHLD|
* 0x0000   0x3    |   0    0    0     0  |   1   0    1     0  |  0     0   0   0
* WRSETUP=Write setup width.number of clk cycles
* WRSTRB=Write strobe width(/AWE).
* WRHLD=Write hold width.(EA,/BE)
* RDSETUP=Read setup width.
* 
************************************************************************************/
#define DEVCR      0x19c0200 
/* Define McBSP0 Registers */
#define McBSP0_DRR      0x18c0000   /* Address of data receive reg.         */
#define McBSP0_DXR      0x18c0004   /* Address of data transmit reg.        */
#define McBSP0_SPCR     0x18c0008   /* Address of serial port contl. reg.   */
#define McBSP0_RCR      0x18c000C   /* Address of receive control reg.      */
#define McBSP0_XCR      0x18c0010   /* Address of transmit control reg.     */
#define McBSP0_SRGR     0x18c0014   /* Address of sample rate generator     */
#define McBSP0_MCR      0x18c0018   /* Address of multichannel reg.         */
#define McBSP0_RCER     0x18c001C   /* Address of receive channel enable.   */
#define McBSP0_XCER     0x18c0020   /* Address of transmit channel enable.  */
#define McBSP0_PCR      0x18c0024   /* Address of pin control reg.          */

/* Define McBSP1 Registers */
#define McBSP1_DRR      0x1900000   /* Address of data receive reg.         */
#define McBSP1_DXR      0x1900004   /* Address of data transmit reg.        */
#define McBSP1_SPCR     0x1900008   /* Address of serial port contl. reg.   */
#define McBSP1_RCR      0x190000C   /* Address of receive control reg.      */
#define McBSP1_XCR      0x1900010   /* Address of transmit control reg.     */
#define McBSP1_SRGR     0x1900014   /* Address of sample rate generator     */
#define McBSP1_MCR      0x1900018   /* Address of multichannel reg.         */
#define McBSP1_RCER     0x190001C   /* Address of receive channel enable.   */
#define McBSP1_XCER     0x1900020   /* Address of transmit channel enable.  */
#define McBSP1_PCR      0x1900024   /* Address of pin control reg.          */

/* Define L2 Cache Registers */
/*  Not completed  */
#define L2CFG           0x1840000   /* Address of L2 config reg             */
#define MAR0            0x1848200   /* Address of mem attribute reg. Control CE0         */

/* Define Interrupt Registers */
#define IMH             0x19c0000   /* Address of Interrupt Multiplexer High*/
#define IML             0x19c0004   /* Address of Interrupt Multiplexer Low */
#define IPOL            0x19c0008   /* Address of Interrupt Polarity */

/*Define Device Registers  */
#define  DEVCFG         0x19c0200    /*Address of Device Configuration */

/* Define Timer0 Registers */
#define TIMER0_CTRL     0x1940000	/* Address of timer0 control reg.       */
#define TIMER0_PRD      0x1940004	/* Address of timer0 period reg.        */
#define TIMER0_COUNT    0x1940008	/* Address of timer0 counter reg.       */

/* Define Timer1 Registers */
#define TIMER1_CTRL     0x1980000	/* Address of timer1 control reg.       */
#define TIMER1_PRD      0x1980004	/* Address of timer1 period reg.        */
#define TIMER1_COUNT    0x1980008	/* Address of timer1 counter reg.       */

/* Define EDMA Registers */
#define ESEL0			0x01A0FF00	/* Address of EDMA event selector 0    */
#define ESEL1			0x01A0FF04	/* Address of EDMA event selector 1    */
#define ESEL3			0x01A0FF0C	/* Address of EDMA event selector 3    */
#define PQSR			0x01A0FFE0	/* Address of priority queue status     */
#define CIPR			0x01A0FFE4	/* Address of channel interrupt pending */
#define CIER			0x01A0FFE8	/* Address of channel interrupt enable  */
#define CCER			0x01A0FFEC	/* Address of channel chain enable      */
#define ER				0x01A0FFF0	/* Address of event register            */
#define EER				0x01A0FFF4	/* Address of event enable register     */
#define ECR				0x01A0FFF8	/* Address of event clear register      */
#define ESR				0x01A0FFFC	/* Address of event set register        */

/* Define EDMA Transfer Parameter Entry Fields */
#define OPT				0*4			/* Options Parameter                    */
#define SRC				1*4			/* SRC Address Parameter                */
#define CNT				2*4			/* Count Parameter                      */
#define DST				3*4			/* DST Address Parameter                */
#define IDX				4*4			/* IDX Parameter                        */
#define LNK				5*4			/* LNK Parameter                        */
						
/* Define EDMA Parameter RAM Addresses */ 
#define EVENT0_PARAMS 0x01A00000
#define EVENT1_PARAMS EVENT0_PARAMS + 0x18
#define EVENT2_PARAMS EVENT1_PARAMS + 0x18
#define EVENT3_PARAMS EVENT2_PARAMS + 0x18
#define EVENT4_PARAMS EVENT3_PARAMS + 0x18
#define EVENT5_PARAMS EVENT4_PARAMS + 0x18
#define EVENT6_PARAMS EVENT5_PARAMS + 0x18
#define EVENT7_PARAMS EVENT6_PARAMS + 0x18
#define EVENT8_PARAMS EVENT7_PARAMS + 0x18
#define EVENT9_PARAMS EVENT8_PARAMS + 0x18
#define EVENTA_PARAMS EVENT9_PARAMS + 0x18
#define EVENTB_PARAMS EVENTA_PARAMS + 0x18
#define EVENTC_PARAMS EVENTB_PARAMS + 0x18
#define EVENTD_PARAMS EVENTC_PARAMS + 0x18
#define EVENTE_PARAMS EVENTD_PARAMS + 0x18
#define EVENTF_PARAMS EVENTE_PARAMS + 0x18
#define EVENTN_PARAMS EVENTF_PARAMS + 0x18
#define EVENTO_PARAMS EVENTN_PARAMS + 0x18

/* Define QDMA Memory Mapped Registers */
#define QDMA_OPT		0x02000000	/* Address of QDMA options register     */
#define QDMA_SRC		0x02000004	/* Address of QDMA SRC address register */
#define QDMA_CNT		0x02000008	/* Address of QDMA counts register      */
#define QDMA_DST		0x0200000C	/* Address of QDMA DST address register */
#define QDMA_IDX		0x02000010	/* Address of QDMA index register       */

 
/* Define QDMA Pseudo Registers */
#define QDMA_S_OPT		0x02000020	/* Address of QDMA options register     */
#define QDMA_S_SRC		0x02000024	/* Address of QDMA SRC address register */
#define QDMA_S_CNT		0x02000028	/* Address of QDMA counts register      */
#define QDMA_S_DST		0x0200002C	/* Address of QDMA DST address register */
#define QDMA_S_IDX		0x02000030	/* Address of QDMA index register       */

/* Definitions for the DSK Board and SW */
/* Only for reference */
#define PI				3.1415926
#define IO_PORT			0x90080000  /* I/O port Address,top byte valid data */
#define INTERNAL_MEM_SIZE 0x08
#define EXTERNAL_MEM_SIZE 0x10
#define FLASH_SIZE		0x20000 
#define POST_SIZE		0x10000 
#define FLASH_WRITE_SIZE 0x80 
#define INTERNAL_MEM_START 0x12000
#define EXTERNAL_MEM_START 0x80000000
#define FLASH_START		0x90000000
#define POST_END		0x90010000 
#define FLASH_KEY1		0xAA
#define FLASH_KEY2		0x55
#define FLASH_KEY3		0xA0
#define ALL_A			0xaaaaaaaa
#define ALL_5			0x55555555
#define ALT_A5			0xa5a5a5a5
#define ALT_5A			0x5a5a5a5a
#define CE1_8			0xffffff03  /* reg to set CE1 as 8bit async */
#define CE1_32			0xffffff23  /* reg to set CE1 as 32bit async */


/*Define PLL Control Registers */
#define PLLPID		    0x01B7C000	/* Address of Peripheral identification register */
#define PLLCSR		    0x01B7C100	/* Address of PLL control/status  register     */
#define PLLM		    0x01B7C110	/* Address of PLL mulitiplier control register     */
#define PLLDIV0		    0x01B7C114	/* Address of PLL controller divider 0 register     */
#define PLLDIV1         0x01B7C118	/* Address of PLL controller divider 1 register     */
#define PLLDIV2		    0x01B7C11C	/* Address of PLL controller divider 2 register     */
#define PLLDIV3		    0x01B7C120	/* Address of PLL controller divider 3 register     */
#define OSCDIV1		    0x01B7C124	/* Address of osciliator divder 1 register     */
/*Define I2C0   Registers*/
/*Define HPI Registers*/
/*Define GPIO Registers*/
#define GPEN		    0x01B00000	/* Address of GPIO enable register     */
#define GPDIR		    0x01B00004	/* Address of GPIO direction register     */
#define GPVAL		    0x01B00008	/* Address of GPIO value register     */
#define GPDH		    0x01B00010	/* Address of GPIO delta high register     */
#define GPHM		    0x01B00014	/* Address of GPIO high mask register     */
#define GPDL		    0x01B00018	/* Address of GPIO delta low register     */
#define GPLM		    0x01B0001C	/* Address of GPIO low mask register     */
#define GPGC		    0x01B00020	/* Address of GPIO global control register     */
#define GPPOL		    0x01B00024	/* Address of GPIO interrupt polarity register     */