user_emifa.h

6416 emif flash 引导烧写程序

/****************************************************************/
/*    EMIFA.H                       *****************************/
/*  MACRO FUNCTIONS:                                          */
/*    SDRAM_REFRESH_ENABLE()  - Enable SDRAM refresh cycles      */
/*    SDRAM_REFRESH_DISABLE() - Disable SDRAM refresh cycles     */
/*    SDRAM_REFRESH_PERIOD()  - Assigns refresh period for SDRAM */
/*    SDRAM_INT()             */
/*    EMIFA_GET_MAP_MODE()  */
/*                                       */
/*  FUNCTIONS:  */
/*    emifa_init()*/
/**********************   EMIFA REGISTERS  ********************/
         
#define  EMIFA_GCTRL_ADDR       0x01800000   /*EMIFA GBLCTL ADDRESS*/
#define  EMIFA_CE0_CTRL_ADDR    0x01800008
#define  EMIFA_CE1_CTRL_ADDR    0x01800004
#define  EMIFA_CE2_CTRL_ADDR    0x01800010
#define  EMIFA_CE3_CTRL_ADDR    0x01800014
#define  EMIFA_SDRAM_CTRL_ADDR  0x01800018
#define  EMIFA_SDRAM_REF_ADDR   0x0180001C
#define  EMIFA_SDRAM_EXT_ADDR   0x01800020 
/*#define  EMIFA_CESEC1_ADDR  0x01800044
#define  EMIFA_CESEC0_ADDR  0x01800048 */
#define  EMIFA_GCTRL     (EMIFA_GCTRL_ADDR)
#define  EMIFA_CE0_CTRL  (EMIFA_CE0_CTRL_ADDR)
#define  EMIFA_CE1_CTRL  (EMIFA_CE1_CTRL_ADDR)
#define  EMIFA_CE2_CTRL  (EMIFA_CE2_CTRL_ADDR)
#define  EMIFA_CE3_CTRL  (EMIFA_CE3_CTRL_ADDR)
#define  EMIFA_SDRAM_CTRL(EMIFA_SDRAM_CTRL_ADDR)
#define  EMIFA_SDRAM_REF (EMIFA_SDRAM_REF_ADDR)
#define  EMIFA_SDRAM_EXT (EMIFA_SDRAM_EXT_ADDR)

/*C64XEMIF Global Control Register Bits  */
#define  CLK6EN      3
#define  CLK4EN      4
#define  EK1EN       5
#define  EK1HZ       6
#define  BRMODE     13
#define  EK2HZ      17
#define  EK2RATE    18
/*C64XEMIF CE Space Control Register Bits  */
#define  READ_HOLD         0
#define  READ_HOLD_SZ      3
#define  WRITE_HOLD_MSB    3
#define  MTYPE             4
#define  MTYPE_SZ          3
#define  READ_STROBE       8
#define  READ_STROBE_SZ    6
#define  TA               14
#define  TA_SZ             2
#define  READ_SETUP       16
#define  READ_SETUP_SZ     4
#define  WRITE_HOLD       20
#define  WRITE_HOLD_SZ     2
#define  WRITE_STROBE     22
#define  WRITE_STROBE_SZ   6
#define  WRITE_SETUP      28
#define  WRITE_SETUP_SZ    2
/*SDRAM Control Register    */
#define  SLFRFR       0  
#define  TRC         12
#define  TRC_SZ       4
#define  TRP         16
#define  TRP_SZ       4
#define  TRCD        20
#define  TRCD_SZ      4
#define  INIT        24
#define  RFEN        25
#define  SDCSZ       26
#define  SDCSZ_SZ     2
#define  SDRSZ       28
#define  SDRSZ_SZ     2
#define  SDBSZ       30
/*EMIF SDRAM Timing Register    */
#define  PERIOD       0
#define  PERIOD_SZ   12
#define  COUNTER     12
#define  COUNTER_SZ  12
#define  XRFR        24
#define  XRFR_SZ      2
/*C64X SDRAM Extension Register  */
#define  TCL       0
#define  TRAS      1
#define  TRAS_SZ   3
#define  TRRD      4
#define  TWR       5
#define  TWR_SZ    2
  

/*   MACRO FUNCTIONS                    */\
/*
#define SDRAM_REFRESH_ENABLE()  SET_BIT(EMIFA_SDRAM_CTRL_ADDR,REFN)
#define SDRAM_REFRESH_DISABLE()  RESET_BIT(EMIFA_SDRAM_CTRL_ADDR,REFN)        
#define SDRAM_INT()  SET_BIT(EMIFA_SDRAM_CTRL_ADDR,INIT)
#define SDRAM_TCL()  SET_REG(EMIFA_SDRAM_EXT_ADDR,TCL)


#define SDRAM_REFRESH_ENABLE() 
  *(volatile unsigned int*)EMIFA_SDRAM_CTRL_ADDR|=REFN
#define SDRAM_REFRESH_DISABLE() 
   *(volatile unsigned int*)EMIFA_SDRAM_CTRL_ADDR|=REFN        
#define SDRAM_INT()  
   *(volatile unsigned int*)EMIFA_SDRAM_CTRL_ADDR|=INIT
#define SDRAM_TCL()  
   *(volatile unsigned int*)EMIFA_SDRAM_EXT_ADDR=TCL)

*/
void emifa_init(unsigned int g_ctrl,
                unsigned int ce0_ctrl,
                unsigned int ce1_ctrl,
                unsigned int ce2_ctrl,
                unsigned int ce3_ctrl,
                unsigned int sdram_ctrl,
                unsigned int sdram_refresh
                )
{
   /*REG_WRITE(EMIFA_GCTRL_ADDR, g_ctrl);
   REG_WRITE(EMIFA_CE0_CTRL_ADDR, ce0_ctrl);
   REG_WRITE(EMIFA_CE1_CTRL_ADDR, ce1_ctrl);
   REG_WRITE(EMIFA_CE2_CTRL_ADDR, ce2_ctrl);
   REG_WRITE(EMIFA_CE3_CTRL_ADDR, ce3_ctrl);
   REG_WRITE(EMIFA_SDRAM_CTRL_ADDR, sdram_ctrl); 
   REG_WRITE(EMIFA_SDRAM_EXT_ADDR, sdram_refresh);*/
   
   *(volatile unsigned int*) EMIFA_GCTRL_ADDR|= g_ctrl;
   *(volatile unsigned int*) EMIFA_CE0_CTRL_ADDR= ce0_ctrl;
   *(volatile unsigned int*) EMIFA_CE1_CTRL_ADDR= ce1_ctrl;
   *(volatile unsigned int*) EMIFA_CE2_CTRL_ADDR= ce2_ctrl;
   *(volatile unsigned int*) EMIFA_CE3_CTRL_ADDR= ce3_ctrl;
   *(volatile unsigned int*) EMIFA_SDRAM_CTRL_ADDR= sdram_ctrl; 
   *(volatile unsigned int*) EMIFA_SDRAM_EXT_ADDR= sdram_refresh;
   
   
}