can_top.vhd

free hardware ip core about sparcv8,a soc cpu in vhdl

                  IF ((((wr AND release_buffer) AND (NOT fifo_full)) AND (NOT fifo_empty)) = '1') THEN
                     fifo_cnt <= fifo_cnt - ("000" & length_info) + "0000001" ;    
                  END IF;
               END IF;
            END IF;
         END IF;
      END IF;
   END PROCESS;
   fifo_full <= CONV_STD_LOGIC(fifo_cnt = "1000000") ;
   fifo_empty <= CONV_STD_LOGIC(fifo_cnt = "0000000") ;

   -- Counting data in length_fifo and overrun_info fifo
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         info_cnt_xhdl4 <= "0000000" ;    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (reset_mode = '1') THEN
            info_cnt_xhdl4 <= "0000000" ;    
         ELSE
            IF ((write_length_info XOR release_buffer) = '1') THEN
               IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
                  info_cnt_xhdl4 <= info_cnt_xhdl4 - "0000001" ;    
               ELSE
                  IF ((write_length_info AND (NOT info_full)) = '1') THEN
                     info_cnt_xhdl4 <= info_cnt_xhdl4 + "0000001" ;    
                  END IF;
               END IF;
            END IF;
         END IF;
      END IF;
   END PROCESS;
   info_full <= CONV_STD_LOGIC(info_cnt_xhdl4 = "1000000") ;
   info_empty_xhdl3 <= CONV_STD_LOGIC(info_cnt_xhdl4 = "0000000") ;

   -- Selecting which address will be used for reading data from rx fifo
   
   PROCESS (extended_mode, rd_pointer, addr)
      VARIABLE read_address_xhdl18  : std_logic_vector(5 DOWNTO 0);
   BEGIN
      IF (extended_mode = '1') THEN
         -- extended mode
         
         read_address_xhdl18 := rd_pointer + (addr - "010000");    
      ELSE
         -- normal mode
         
         read_address_xhdl18 := rd_pointer + (addr - "010100");    
      END IF;
      read_address <= read_address_xhdl18;
   END PROCESS;

   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         initialize_memories <= '1';    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (andv(wr_info_pointer) = '1') THEN
            initialize_memories <= '0' ;    
         END IF;
      END IF;
   END PROCESS;
   -- port connections for Ram
   --64x8
   data_out_xhdl1 <= q_dp_64x8 ;
   data_64x8_xhdl5 <= data_in ;
   wren_64x8_xhdl6 <= wr AND (NOT fifo_full) ;
   rden_64x8_xhdl7 <= fifo_selected ;
   wraddress_64x8_xhdl8 <= wr_pointer ;
   rdaddress_64x8_xhdl9 <= read_address ;
   --64x4
   length_info <= q_dp_64x4 ;
   data_64x4_xhdl10 <= len_cnt AND NOT initialize_memories & NOT initialize_memories & NOT initialize_memories & NOT initialize_memories ;
   wren_64x4x1_xhdl11 <= (write_length_info AND (NOT info_full)) OR initialize_memories ;
   wraddress_64x4x1_xhdl12 <= wr_info_pointer ;
   rdaddress_64x4x1_xhdl13 <= rd_info_pointer ;
   --64x1
   overrun_xhdl2 <= q_dp_64x1 ;
   data_64x1_xhdl14 <= (latch_overrun OR (wr AND fifo_full)) AND (NOT initialize_memories) ;
   -- `ifdef ALTERA_RAM
   -- //  altera_ram_64x8_sync fifo
   --   lpm_ram_dp fifo
   --   (
   --     .q         (data_out),
   --     .rdclock   (clk),
   --     .wrclock   (clk),
   --     .data      (data_in),
   --     .wren      (wr & (~fifo_full)),
   --     .rden      (fifo_selected),
   --     .wraddress (wr_pointer),
   --     .rdaddress (read_address)
   --   );
   --   defparam fifo.lpm_width = 8;
   --   defparam fifo.lpm_widthad = 6;
   --   defparam fifo.lpm_numwords = 64;
   -- 
   -- 
   -- //  altera_ram_64x4_sync info_fifo
   --   lpm_ram_dp info_fifo
   --   (
   --     .q         (length_info),
   --     .rdclock   (clk),
   --     .wrclock   (clk),
   --     .data      (len_cnt & {4{~initialize_memories}}),
   --     .wren      (write_length_info & (~info_full) | initialize_memories),
   --     .wraddress (wr_info_pointer),
   --     .rdaddress (rd_info_pointer)
   --   );
   --   defparam info_fifo.lpm_width = 4;
   --   defparam info_fifo.lpm_widthad = 6;
   --   defparam info_fifo.lpm_numwords = 64;
   -- 
   -- 
   -- //  altera_ram_64x1_sync overrun_fifo
   --   lpm_ram_dp overrun_fifo
   --   (
   --     .q         (overrun),
   --     .rdclock   (clk),
   --     .wrclock   (clk),
   --     .data      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
   --     .wren      (write_length_info & (~info_full) | initialize_memories),
   --     .wraddress (wr_info_pointer),
   --     .rdaddress (rd_info_pointer)
   --   );
   --   defparam overrun_fifo.lpm_width = 1;
   --   defparam overrun_fifo.lpm_widthad = 6;
   --   defparam overrun_fifo.lpm_numwords = 64;

END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53  Aug. 1, 2005 
-- Tue Aug  9 07:33:51 2005
--
--      Input file         : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
--      Design name        : can_crc
--      Author             : 
--      Company            : Actel
--
--      Description        : 
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--//                                                              ////
--//  can_crc.v                                                   ////
--//                                                              ////
--//                                                              ////
--//  This file is part of the CAN Protocol Controller            ////
--//  http://www.opencores.org/projects/can/                      ////
--//                                                              ////
--//                                                              ////
--//  Author(s):                                                  ////
--//       Igor Mohor                                             ////
--//       [e-mail]                                    ////
--//                                                              ////
--//                                                              ////
--//  All additional information is available in the README.txt   ////
--//  file.                                                       ////
--//                                                              ////
--////////////////////////////////////////////////////////////////////
--//                                                              ////
--// Copyright (C) 2002, 2003, 2004 Authors                       ////
--//                                                              ////
--// This source file may be used and distributed without         ////
--// restriction provided that this copyright statement is not    ////
--// removed from the file and that any derivative work contains  ////
--// the original copyright notice and the associated disclaimer. ////
--//                                                              ////
--// This source file is free software; you can redistribute it   ////
--// and/or modify it under the terms of the GNU Lesser General   ////
--// Public License as published by the Free Software Foundation; ////
--// either version 2.1 of the License, or (at your option) any   ////
--// later version.                                               ////
--//                                                              ////
--// This source is distributed in the hope that it will be       ////
--// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
--// PURPOSE.  See the GNU Lesser General Public License for more ////
--// details.                                                     ////
--//                                                              ////
--// You should have received a copy of the GNU Lesser General    ////
--// Public License along with this source; if not, download it   ////
--// from http://www.opencores.org/lgpl.shtml                     ////
--//                                                              ////
--// The CAN protocol is developed by Robert Bosch GmbH and       ////
--// protected by patents. Anybody who wants to implement this    ////
--// CAN IP core on silicon has to obtain a CAN protocol license  ////
--// from Bosch.                                                  ////
--//                                                              ////
--////////////////////////////////////////////////////////////////////
--
-- CVS Revision History
--
-- $Log: can_crc.v,v $
-- Revision 1.5  2004/02/08 14:25:57  mohor
-- Header changed.
--
-- Revision 1.4  2003/07/16 13:16:51  mohor
-- Fixed according to the linter.
--
-- Revision 1.3  2003/02/10 16:02:11  mohor
-- CAN is working according to the specification. WB interface and more
-- registers (status, IRQ, ...) needs to be added.
--
-- Revision 1.2  2003/02/09 02:24:33  mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.1  2003/01/08 02:10:54  mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;

ENTITY can_crc IS
   PORT (
      clk                     : IN std_logic;   
      data                    : IN std_logic;   
      enable                  : IN std_logic;   
      initialize              : IN std_logic;   
      crc                     : OUT std_logic_vector(14 DOWNTO 0));   
END ENTITY can_crc;

ARCHITECTURE RTL OF can_crc IS

   TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);

   SIGNAL crc_next                 :  std_logic;   
   SIGNAL crc_tmp                  :  std_logic_vector(14 DOWNTO 0);   
   SIGNAL crc_xhdl1                :  std_logic_vector(14 DOWNTO 0);   

BEGIN
   crc <= crc_xhdl1;
   crc_next <= data XOR crc_xhdl1(14) ;
   crc_tmp <= crc_xhdl1(13 DOWNTO 0) & '0' ;

   PROCESS (clk)
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
         IF (initialize = '1') THEN
            crc_xhdl1 <= "000000000000000";    
         ELSE
            IF (enable = '1') THEN
               IF (crc_next = '1') THEN
                  crc_xhdl1 <= crc_tmp XOR "100010110011001";    
               ELSE
                  crc_xhdl1 <= crc_tmp ;    
               END IF;
            END IF;
         END IF;
      END IF;
   END PROCESS;

END ARCHITECTURE RTL;
----------------------------------------------------------------------------------------------
--
-- VHDL file generated by X-HDL - Revision 3.2.53  Aug. 1, 2005 
-- Tue Aug  9 07:33:51 2005
--
--      Input file         : C:/Documents and Settings/BryantI/My Documents/tmp/can_top.v
--      Design name        : can_ibo
--      Author             : 
--      Company            : Actel
--
--      Description        : 
--
--
----------------------------------------------------------------------------------------------
--
--////////////////////////////////////////////////////////////////////
--//                                                              ////
--//  can_ibo.v                                                   ////
--//                                                              ////
--//                                                              ////
--//  This file is part of the CAN Protocol Controller            ////
--//  http://www.opencores.org/projects/can/                      ////
--//                                                              ////
--//