can_top.vhd

free hardware ip core about sparcv8,a soc cpu in vhdl

--
-- Revision 1.17  2003/06/27 20:56:15  simons
-- Virtual silicon ram instances added.
--
-- Revision 1.16  2003/06/18 23:03:44  mohor
-- Typo fixed.
--
-- Revision 1.15  2003/06/11 09:37:05  mohor
-- overrun and length_info fifos are initialized at the end of reset.
--
-- Revision 1.14  2003/03/05 15:02:30  mohor
-- Xilinx RAM added.
--
-- Revision 1.13  2003/03/01 22:53:33  mohor
-- Actel APA ram supported.
--
-- Revision 1.12  2003/02/19 14:44:03  mohor
-- CAN core finished. Host interface added. Registers finished.
-- Synchronization to the wishbone finished.
--
-- Revision 1.11  2003/02/14 20:17:01  mohor
-- Several registers added. Not finished, yet.
--
-- Revision 1.10  2003/02/11 00:56:06  mohor
-- Wishbone interface added.
--
-- Revision 1.9  2003/02/09 02:24:33  mohor
-- Bosch license warning added. Error counters finished. Overload frames
-- still need to be fixed.
--
-- Revision 1.8  2003/01/31 01:13:38  mohor
-- backup.
--
-- Revision 1.7  2003/01/17 17:44:31  mohor
-- Fifo corrected to be synthesizable.
--
-- Revision 1.6  2003/01/15 13:16:47  mohor
-- When a frame with "remote request" is received, no data is stored
-- to fifo, just the frame information (identifier, ...). Data length
-- that is stored is the received data length and not the actual data
-- length that is stored to fifo.
--
-- Revision 1.5  2003/01/14 17:25:09  mohor
-- Addresses corrected to decimal values (previously hex).
--
-- Revision 1.4  2003/01/14 12:19:35  mohor
-- rx_fifo is now working.
--
-- Revision 1.3  2003/01/09 21:54:45  mohor
-- rx fifo added. Not 100 % verified, yet.
--
-- Revision 1.2  2003/01/09 14:46:58  mohor
-- Temporary files (backup).
--
-- Revision 1.1  2003/01/08 02:10:55  mohor
-- Acceptance filter added.
--
--
--
--
-- synopsys translate_off
--`include "can_defines.v"
-- synopsys translate_on

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;

ENTITY can_fifo IS
   PORT (
      clk                     : IN std_logic;   
      rst                     : IN std_logic;   
      wr                      : IN std_logic;   
      data_in                 : IN std_logic_vector(7 DOWNTO 0);   
      addr                    : IN std_logic_vector(5 DOWNTO 0);   
      data_out                : OUT std_logic_vector(7 DOWNTO 0);   
      fifo_selected           : IN std_logic;   
      reset_mode              : IN std_logic;   
      release_buffer          : IN std_logic;   
      extended_mode           : IN std_logic;   
      overrun                 : OUT std_logic;   
      info_empty              : OUT std_logic;   
      info_cnt                : OUT std_logic_vector(6 DOWNTO 0);   
      --------------------------------------------------
-- port connections for Ram
--64x8

      q_dp_64x8               : IN std_logic_vector(7 DOWNTO 0);   
      data_64x8               : OUT std_logic_vector(7 DOWNTO 0);   
      wren_64x8               : OUT std_logic;   
      rden_64x8               : OUT std_logic;   
      wraddress_64x8          : OUT std_logic_vector(5 DOWNTO 0);   
      rdaddress_64x8          : OUT std_logic_vector(5 DOWNTO 0);   
      --64x4

      q_dp_64x4               : IN std_logic_vector(3 DOWNTO 0);   
      data_64x4               : OUT std_logic_vector(3 DOWNTO 0);   
      wren_64x4x1             : OUT std_logic;   
      wraddress_64x4x1        : OUT std_logic_vector(5 DOWNTO 0);   
      rdaddress_64x4x1        : OUT std_logic_vector(5 DOWNTO 0);   
      --64x1

      q_dp_64x1               : IN std_logic;   
      data_64x1               : OUT std_logic);   
END ENTITY can_fifo;

ARCHITECTURE RTL OF can_fifo IS

   TYPE xhdl_15 IS ARRAY (0 TO 63) OF std_logic_vector(7 DOWNTO 0);
   TYPE xhdl_16 IS ARRAY (0 TO 63) OF std_logic_vector(3 DOWNTO 0);
   TYPE xhdl_17 IS ARRAY (0 TO 63) OF std_logic;
   TYPE xhdl_46 IS ARRAY (0 TO 7) OF std_logic_vector(7 DOWNTO 0);

   --------------------------------------------------
   SIGNAL fifo                     :  xhdl_15;   
   SIGNAL length_fifo              :  xhdl_16;   
   SIGNAL overrun_info             :  xhdl_17;   
   SIGNAL rd_pointer               :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL wr_pointer               :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL read_address             :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL wr_info_pointer          :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL rd_info_pointer          :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL wr_q                     :  std_logic;   
   SIGNAL len_cnt                  :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL fifo_cnt                 :  std_logic_vector(6 DOWNTO 0);   
   SIGNAL latch_overrun            :  std_logic;   
   SIGNAL initialize_memories      :  std_logic;   
   SIGNAL length_info              :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL write_length_info        :  std_logic;   
   SIGNAL fifo_empty               :  std_logic;   
   SIGNAL fifo_full                :  std_logic;   
   SIGNAL info_full                :  std_logic;   
   SIGNAL data_out_xhdl1           :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL overrun_xhdl2            :  std_logic;   
   SIGNAL info_empty_xhdl3         :  std_logic;   
   SIGNAL info_cnt_xhdl4           :  std_logic_vector(6 DOWNTO 0);   
   SIGNAL data_64x8_xhdl5          :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL wren_64x8_xhdl6          :  std_logic;   
   SIGNAL rden_64x8_xhdl7          :  std_logic;   
   SIGNAL wraddress_64x8_xhdl8     :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL rdaddress_64x8_xhdl9     :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL data_64x4_xhdl10         :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL wren_64x4x1_xhdl11       :  std_logic;   
   SIGNAL wraddress_64x4x1_xhdl12  :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL rdaddress_64x4x1_xhdl13  :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL data_64x1_xhdl14         :  std_logic;   

BEGIN
   data_out <= data_out_xhdl1;
   overrun <= overrun_xhdl2;
   info_empty <= info_empty_xhdl3;
   info_cnt <= info_cnt_xhdl4;
   data_64x8 <= data_64x8_xhdl5;
   wren_64x8 <= wren_64x8_xhdl6;
   rden_64x8 <= rden_64x8_xhdl7;
   wraddress_64x8 <= wraddress_64x8_xhdl8;
   rdaddress_64x8 <= rdaddress_64x8_xhdl9;
   data_64x4 <= data_64x4_xhdl10;
   wren_64x4x1 <= wren_64x4x1_xhdl11;
   wraddress_64x4x1 <= wraddress_64x4x1_xhdl12;
   rdaddress_64x4x1 <= rdaddress_64x4x1_xhdl13;
   data_64x1 <= data_64x1_xhdl14;
   write_length_info <= (NOT wr) AND wr_q ;

   -- Delayed write signal
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         wr_q <= '0' ;    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (reset_mode = '1') THEN
            wr_q <= '0' ;    
         ELSE
            wr_q <= wr ;    
         END IF;
      END IF;
   END PROCESS;

   -- length counter
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         len_cnt <= "0000";    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF ((reset_mode OR write_length_info) = '1') THEN
            len_cnt <= "0000" ;    
         ELSE
            IF ((wr AND (NOT fifo_full)) = '1') THEN
               len_cnt <= len_cnt + "0001" ;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   -- wr_info_pointer
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         wr_info_pointer <= "000000";    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (((write_length_info AND (NOT info_full)) OR initialize_memories) = '1') THEN
            wr_info_pointer <= wr_info_pointer + "000001" ;    
         ELSE
            IF (reset_mode = '1') THEN
               wr_info_pointer <= rd_info_pointer ;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   -- rd_info_pointer
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         rd_info_pointer <= "000000";    
      ELSIF (clk'EVENT AND clk = '1') THEN
        IF ((release_buffer AND (NOT info_empty_xhdl3)) = '1') THEN
--      Fix from opencores rev 1.28
--      IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
            rd_info_pointer <= rd_info_pointer + "000001" ;    
         END IF;
      END IF;
   END PROCESS;

   -- rd_pointer
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         rd_pointer <= "000000";    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF ((release_buffer AND (NOT fifo_empty)) = '1') THEN
            rd_pointer <= rd_pointer + ("00" & length_info) ;    
         END IF;
      END IF;
   END PROCESS;

   -- wr_pointer
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         wr_pointer <= "000000";    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (reset_mode = '1') THEN
            wr_pointer <= rd_pointer ;    
         ELSE
            IF ((wr AND (NOT fifo_full)) = '1') THEN
               wr_pointer <= wr_pointer + "000001" ;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   -- latch_overrun
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         latch_overrun <= '0';    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF ((reset_mode OR write_length_info) = '1') THEN
            latch_overrun <= '0' ;    
         ELSE
            IF ((wr AND fifo_full) = '1') THEN
               latch_overrun <= '1' ;    
            END IF;
         END IF;
      END IF;
   END PROCESS;

   -- Counting data in fifo
   
   PROCESS (clk, rst)
   BEGIN
      IF (rst = '1') THEN
         fifo_cnt <= "0000000";    
      ELSIF (clk'EVENT AND clk = '1') THEN
         IF (reset_mode = '1') THEN
            fifo_cnt <= "0000000" ;    
         ELSE
            IF (((wr AND (NOT release_buffer)) AND (NOT fifo_full)) = '1') THEN
               fifo_cnt <= fifo_cnt + "0000001" ;    
            ELSE
               IF ((((NOT wr) AND release_buffer) AND (NOT fifo_empty)) = '1') THEN
                  fifo_cnt <= fifo_cnt - ("000" & length_info) ;    
               ELSE