ata_device.v

free hardware ip core about sparcv8,a soc cpu in vhdl

         M4_DoutSetup   = 20,       // T5
         M4_DoutHold = 5,        // T6
            M4_AddrHold = 10;       // T9



   /////////////////////////////////////////////////////
   // ATA Mode 0 Timing                               //
   /////////////////////////////////////////////////////

   // Output Delay Path
   if(mode==0) (ata_dior_n => ata_data) = //(01,10,0z,z1,1z,z0)
               (0,0,
               M0_DoutHold, (M0_DioHigh - M0_DoutSetup),
               M0_DoutHold, (M0_DioHigh - M0_DoutSetup) );

   // Write Data Setup/Hold Check
   $setuphold(negedge ata_diow, ata_data, M0_WrSetup, M0_WrHold, , ,ata_rst_m0 );

   // DioX Active time Check
   $width(posedge ata_dior &&& ata_rst_m0, M0_DioHigh );
   $width(posedge ata_diow &&& ata_rst_m0, M0_DioHigh );

   // DioX Min Cycle Width Check
   $period(posedge ata_dior &&& ata_rst_m0, M0_DioCycle );
   $period(posedge ata_diow &&& ata_rst_m0, M0_DioCycle );

   // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m0, M0_AddrSetup);

        $hold(ata_da,  negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m0, M0_AddrHold);


   /////////////////////////////////////////////////////
   // ATA Mode 1 Timing                               //
   /////////////////////////////////////////////////////

   // Output Delay Path
   if(mode==1) (ata_dior_n => ata_data) = //(01,10,0z,z1,1z,z0)
               (0,0,
               M1_DoutHold, (M1_DioHigh - M1_DoutSetup),
               M1_DoutHold, (M1_DioHigh - M1_DoutSetup) );

   // Write Data Setup/Hold Check
   $setuphold(negedge ata_diow, ata_data, M1_WrSetup, M1_WrHold, , ,ata_rst_m1 );

   // DioX Active time Check
   $width(posedge ata_dior &&& ata_rst_m1, M1_DioHigh );
   $width(posedge ata_diow &&& ata_rst_m1, M1_DioHigh );

   // DioX Min Cycle Width Check
   $period(posedge ata_dior &&& ata_rst_m1, M1_DioCycle );
   $period(posedge ata_diow &&& ata_rst_m1, M1_DioCycle );

   // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m1, M1_AddrSetup);

        $hold(ata_da,  negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m1, M1_AddrHold);


   /////////////////////////////////////////////////////
   // ATA Mode 2 Timing                               //
   /////////////////////////////////////////////////////

   // Output Delay Path
   if(mode==2) (ata_dior_n => ata_data) = //(01,10,0z,z1,1z,z0)
               (0,0,
               M2_DoutHold, (M2_DioHigh - M2_DoutSetup),
               M2_DoutHold, (M2_DioHigh - M2_DoutSetup) );

   // Write Data Setup/Hold Check
   $setuphold(negedge ata_diow, ata_data, M2_WrSetup, M2_WrHold, , ,ata_rst_m2 );

   // DioX Active time Check
   $width(posedge ata_dior &&& ata_rst_m2, M2_DioHigh );
   $width(posedge ata_diow &&& ata_rst_m2, M2_DioHigh );

   // DioX Min Cycle Width Check
   $period(posedge ata_dior &&& ata_rst_m2, M2_DioCycle );
   $period(posedge ata_diow &&& ata_rst_m2, M2_DioCycle );

   // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m2, M2_AddrSetup);

        $hold(ata_da,  negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m2, M2_AddrHold);

   /////////////////////////////////////////////////////
   // ATA Mode 3 Timing                               //
   /////////////////////////////////////////////////////

   // Output Delay Path
   if(mode==3) (ata_dior_n => ata_data) = //(01,10,0z,z1,1z,z0)
               (0,0,
               M3_DoutHold, (M3_DioHigh - M3_DoutSetup),
               M3_DoutHold, (M3_DioHigh - M3_DoutSetup) );

   // Write Data Setup/Hold Check
   $setuphold(negedge ata_diow, ata_data, M3_WrSetup, M3_WrHold, , ,ata_rst_m3 );

   // DioX Active time Check
   $width(posedge ata_dior &&& ata_rst_m3, M3_DioHigh );
   $width(posedge ata_diow &&& ata_rst_m3, M3_DioHigh );

   $width(negedge ata_dior &&& ata_rst_m3, M3_DioLow );
   $width(negedge ata_diow &&& ata_rst_m3, M3_DioLow );

   // DioX Min Cycle Width Check
   $period(posedge ata_dior &&& ata_rst_m3, M3_DioCycle );
   $period(posedge ata_diow &&& ata_rst_m3, M3_DioCycle );

   // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m3, M3_AddrSetup);

        $hold(ata_da,  negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m3, M3_AddrHold);


   /////////////////////////////////////////////////////
   // ATA Mode 4 Timing                               //
   /////////////////////////////////////////////////////

   // Output Delay Path
   if(mode==4) (ata_dior_n => ata_data) = //(01,10,0z,z1,1z,z0)
               (0,0,
               M4_DoutHold, (M4_DioHigh - M4_DoutSetup),
               M4_DoutHold, (M4_DioHigh - M4_DoutSetup) );

   // Write Data Setup/Hold Check
   $setuphold(negedge ata_diow, ata_data, M4_WrSetup, M4_WrHold, , ,ata_rst_m4 );

   // DioX Active time Check
   $width(posedge ata_dior &&& ata_rst_m4, M4_DioHigh );
   $width(posedge ata_diow &&& ata_rst_m4, M4_DioHigh );

   $width(negedge ata_dior &&& ata_rst_m4, M4_DioLow );
   $width(negedge ata_diow &&& ata_rst_m4, M4_DioLow );

   // DioX Min Cycle Width Check
   $period(posedge ata_dior &&& ata_rst_m4, M4_DioCycle );
   $period(posedge ata_diow &&& ata_rst_m4, M4_DioCycle );

   // Address Setup Hold Checks
        $setup(ata_da,  posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs0, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs1, posedge ata_dior &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_da,  posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs0, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);
        $setup(ata_cs1, posedge ata_diow &&& ata_rst_m4, M4_AddrSetup);

        $hold(ata_da,  negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs0, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs1, negedge ata_dior &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_da,  negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs0, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);
        $hold(ata_cs1, negedge ata_diow &&& ata_rst_m4, M4_AddrHold);



endspecify


endmodule